AT80C51SND1C-ROTUL Atmel, AT80C51SND1C-ROTUL Datasheet - Page 172

• Manufacturer Part Number: AT80C51SND1C-ROTUL
• Description: IC MCU FLASH MP3 DECODER 80-TQFP
• Manufacturer: Atmel
• Series: 80Cr

Specifications of AT80C51SND1C-ROTUL

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, IDE/ATAPI, MMC, SPI, UART/USART, USB
• Peripherals: Audio, I²S, MP3, PCM, POR, WDT
• Number Of I /o: 44
• Program Memory Type: ROMless
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.3 V
• Data Converters: A/D 2x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TQFP, 80-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -

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Registers
AT8xC51SND1C
Table 143. SSCON Register
SSCON (S:93h) – Synchronous Serial Control Register
Reset Value = 0000 0000b
Table 144. SSSTA Register
SSSTA (S:94h) – Synchronous Serial Status Register
Number
SSCR2
SSC4
Bit
7
7
6
5
4
3
2
1
0
7
Mnemonic Description
SSSTO
SSCR2
SSSTA
SSCR1
SSCR0
SSPE
SSPE
SSAA
SSC3
SSI
Bit
6
6
Synchronous Serial Control Rate Bit 2
Refer to Table 136 for rate description.
Synchronous Serial Peripheral Enable Bit
Set to enable the controller.
Clear to disable the controller.
Synchronous Serial Start Flag
Set to send a START condition on the bus.
Clear not to send a START condition on the bus.
Synchronous Serial Stop Flag
Set to send a STOP condition on the bus.
Clear not to send a STOP condition on the bus.
Synchronous Serial Interrupt Flag
Set by hardware when a serial interrupt is requested.
Must be cleared by software to acknowledge interrupt.
Synchronous Serial Assert Acknowledge Flag
Set to enable slave modes. Slave modes are entered when SLA or GCA (if
SSGC set) is recognized.
Clear to disable slave modes.
Master Receiver Mode in progress
Master Transmitter Mode in progress
Slave Receiver Mode in progress
Slave Transmitter Mode in progress
Synchronous Serial Control Rate Bit 1
Refer to Table 136 for rate description.
Synchronous Serial Control Rate Bit 0
Refer to Table 136 for rate description.
SSSTA
SSC2
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
This bit has no specific effect when in master transmitter mode.
Clear to force a not acknowledge (high level on SDA).
Set to force an acknowledge (low level on SDA).
Clear to isolate slave from the bus after last data Byte transmission.
Set to enable slave mode.
5
5
SSSTO
SSC1
4
4
SSC0
SSI
3
3
SSAA
2
2
0
SSCR1
1
1
0
4109L–8051–02/08
SSCR0
0
0
0