ATMEGA645V-8AI Atmel, ATMEGA645V-8AI Datasheet - Page 163
ATMEGA645V-8AI
Manufacturer Part Number
ATMEGA645V-8AI
Description
IC AVR MCU FLASH 64K 1.8V 64TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA325-16MU.pdf
(362 pages)
Specifications of ATMEGA645V-8AI
Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
53
Program Memory Size
64KB (32K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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19.4.1
19.5
2570M–AVR–04/11
USART Initialization
Parity Bit Calculation
Figure 19-4. Frame Formats
be
The frame format used by the USART is set by the UCSZn2:0, UPMn1:0 and USBSn bits in
UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing
the setting of any of these bits will corrupt all ongoing communication for both the Receiver and
Transmitter.
The USART Character SiZe (UCSZn2:0) bits select the number of data bits in the frame. The
USART Parity mode (UPMn1:0) bits enable and set the type of parity bit. The selection between
one or two stop bits is done by the USART Stop Bit Select (USBSn) bit. The Receiver ignores
the second stop bit. An FEn (Frame Error) will therefore only be detected in the cases where the
first stop bit is zero.
The parity bit is calculated by doing an exclusive-or of all the data bits. If odd parity is used, the
result of the exclusive or is inverted. The relation between the parity bit and data bits is as
follows:
If used, the parity bit is located between the last data bit and first stop bit of a serial frame.
The USART has to be initialized before any communication can take place. The initialization pro-
cess normally consists of setting the baud rate, setting frame format and enabling the
Transmitter or the Receiver depending on the usage. For interrupt driven USART operation, the
Global Interrupt Flag should be cleared (and interrupts globally disabled) when doing the
initialization.
St
(n)
P
Sp
IDLE
P
P
d
even
odd
n
(IDLE)
St
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must
high.
Parity bit using even parity
Parity bit using odd parity
Data bit n of the character
P
0
P
even
odd
1
=
=
d
d
2
n 1
n 1
–
–
3
⊕
⊕
…
…
4
⊕
⊕
FRAME
ATmega325/3250/645/6450
[5]
d
d
3
3
⊕
⊕
[6]
d
d
2
2
⊕
⊕
[7]
d
d
1
1
[8]
⊕
⊕
d
d
0
0
[P]
⊕
⊕
0
1
Sp1 [Sp2]
(St / IDLE)
163
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