ATTINY2313V-10PI Atmel, ATTINY2313V-10PI Datasheet - Page 138
![IC AVR MCU FLASH 2K 1.8V 20DIP](/photos/6/80/68043/313-20-dip_sml.jpg)
ATTINY2313V-10PI
Manufacturer Part Number
ATTINY2313V-10PI
Description
IC AVR MCU FLASH 2K 1.8V 20DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY2313V-10PI
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
2KB (1K x 16)
Program Memory Type
FLASH
Eeprom Size
128 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-DIP (0.300", 7.62mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Data Converters
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATTINY2313V-10PI
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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Universal Serial
Interface – USI
Overview
138
ATtiny2313
The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial
communication. Combined with a minimum of control software, the USI allows significantly
higher transfer rates and uses less code space than solutions based on software only. Interrupts
are included to minimize the processor load. The main features of the USI are:
•
•
•
•
•
•
A simplified block diagram of the USI is shown on Figure 60. For the actual placement of I/O
pins, refer to
and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in
the
Figure 60. Universal Serial Interface, Block Diagram
The 8-bit Shift Register is directly accessible via the data bus and contains the incoming and
outgoing data. The register has no buffering so the data must be read as quickly as possible to
ensure that no data is lost. The most significant bit is connected to one of two output pins
depending of the wire mode configuration. A transparent latch is inserted between the serial reg-
ister output and output pin, which delays the change of data output to the opposite clock edge of
the data input sampling. The serial input is always sampled from the Data Input (DI) pin indepen-
dent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the serial register and the counter are clocked simultaneously by the same clock
source. This allows the counter to count the number of bits received or transmitted and generate
an interrupt when the transfer is complete. Note that when an external clock source is selected
the counter counts both clock edges. In this case the counter counts the number of edges, and
not the number of bits. The clock can be selected from three different sources: The USCK pin,
Timer0 overflow, or from software.
Two-wire Synchronous Data Transfer (Master or Slave, f
Three-wire Synchronous Data Transfer (Master, f
Data Received Interrupt
Wake-up from Idle Mode
In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
Two-wire Start Condition Detector with Interrupt Capability
“USI Register Descriptions” on page
“Pinout ATtiny2313” on page
USIDR
USISR
USICR
2
4-bit Counter
3
2
1
0
3
2
1
0
144.
D Q
LE
2. CPU accessible I/O Registers, including I/O bits
[1]
SCKmax
TIM0 OVF
0
1
= f
SCLmax
CK
Two-wire Clock
Control Unit
/2, Slave f
= f
CK
/16)
CLOCK
HOLD
SCKmax
DO
DI/SDA
USCK/SCL
= f
CK
/4)
(Output only)
(Input/Open Drain)
(Input/Open Drain)
2543L–AVR–08/10
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