ATTINY44V-10PU Atmel, ATTINY44V-10PU Datasheet - Page 43
![IC MCU AVR 4K FLASH 10MHZ 14-DIP](/photos/7/39/73953/313-14-dip_sml.jpg)
ATTINY44V-10PU
Manufacturer Part Number
ATTINY44V-10PU
Description
IC MCU AVR 4K FLASH 10MHZ 14-DIP
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY44V-10PU
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
14-DIP (0.300", 7.62mm)
Package
14PDIP
Device Core
AVR
Family Name
ATtiny
Maximum Speed
10 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
12
Interface Type
SPI/USI
On-chip Adc
8-chx10-bit
Number Of Timers
2
For Use With
ATAVRISP2 - PROGRAMMER AVR IN SYSTEM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8.4.1
8.4.1.1
8006K–AVR–10/10
Timed Sequences for Changing the Configuration of the Watchdog Timer
Safety Level 1
The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can
be very helpful when using the Watchdog to wake-up from Power-down.
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in
Sequences for Changing the Configuration of the Watchdog Timer” on page 43
Table 8-1.
Figure 8-7.
The sequence for changing configuration differs slightly between the two safety levels. Separate
procedures are described for each level.
In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit
to one without any restriction. A timed sequence is needed when disabling an enabled Watch-
dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:
WDTON
Unprogrammed
Programmed
1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-
2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits
ten to WDE regardless of the previous value of the WDE bit.
as desired, but with the WDCE bit cleared.
WDT Configuration as a Function of the Fuse Settings of WDTON
Watchdog Timer
Safety
Level
WATCHDOG
1
2
OSCILLATOR
RESET
128 kHz
WDP0
WDP1
WDP2
WDP3
WDE
WDT Initial
State
Disabled
Enabled
Timed sequence
Always enabled
How to Disable the
WDT
MCU RESET
PRESCALER
WATCHDOG
MUX
ATtiny24/44/84
Table 8-1
How to Change Time-
out
No limitations
Timed sequence
for details.
See
“Timed
43
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