ATMEGA1284P-MU Atmel, ATMEGA1284P-MU Datasheet - Page 84
![MCU AVR 128K ISP FLASH 44-QFN](/photos/12/13/121316/313-44-qfn_sml.jpg)
ATMEGA1284P-MU
Manufacturer Part Number
ATMEGA1284P-MU
Description
MCU AVR 128K ISP FLASH 44-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets
1.ATMEGA644PA-PU.pdf
(581 pages)
2.ATMEGA644PA-PU.pdf
(32 pages)
3.ATMEGA1284P-MU.pdf
(20 pages)
Specifications of ATMEGA1284P-MU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
128KB (64K x 16)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-VQFN Exposed Pad
Processor Series
ATMEGA128x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
32
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRRAVEN, ATAVRRZUSBSTICK
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK600 - DEV KIT FOR AVR/AVR32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
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- Download datasheet (27Mb)
164A/164PA/324A/324PA/644A/644PA/1284/1284P
• MOSI/PCINT13 – Port B, Bit 5
MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as a
slave, this pin is configured as an input regardless of the setting of DDB5. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDB5. When the pin is forced
to be an input, the pull-up can still be controlled by the PORTB5 bit.
PCINT13, Pin Change Interrupt source 13: The PB5 pin can serve as an external interrupt
source.
• SS/OC0B/PCINT12 – Port B, Bit 4
SS: Slave Port Select input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDB4. As a slave, the SPI is activated when this pin is driven
low. When the SPI is enabled as a master, the data direction of this pin is controlled by DDB4.
When the pin is forced to be an input, the pull-up can still be controlled by the PORTB4 bit.
OC0B, Output Compare Match B output: The PB4 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB4 set “one”) to
serve this function. The OC0B pin is also the output pin for the PWM mode timer function.
PCINT12, Pin Change Interrupt source 12: The PB4 pin can serve as an external interrupt
source.
• AIN1/OC0A/PCINT11, Bit 3
AIN1, Analog Comparator Negative input. This pin is directly connected to the negative input of
the Analog Comparator.
OC0A, Output Compare Match A output: The PB3 pin can serve as an external output for the
Timer/Counter0 Output Compare. The pin has to be configured as an output (DDB3 set “one”) to
serve this function. The OC0A pin is also the output pin for the PWM mode timer function.
PCINT11, Pin Change Interrupt source 11: The PB3 pin can serve as an external interrupt
source.
• AIN0/INT2/PCINT10, Bit 2
AIN0, Analog Comparator Positive input. This pin is directly connected to the positive input of
the Analog Comparator.
INT2, External Interrupt source 2. The PB2 pin can serve as an External Interrupt source to the
MCU.
PCINT10, Pin Change Interrupt source 10: The PB2 pin can serve as an external interrupt
source.
• T1/CLKO/PCINT9, Bit 1
T1, Timer/Counter1 counter source.
CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The
divided system clock will be output if the CKOUT Fuse is programmed, regardless of the
PORTB1 and DDB1 settings. It will also be output during reset.
PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source.
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