ATMEGA164P-20MCU Atmel, ATMEGA164P-20MCU Datasheet
ATMEGA164P-20MCU
Specifications of ATMEGA164P-20MCU
Related parts for ATMEGA164P-20MCU
ATMEGA164P-20MCU Summary of contents
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... ATmega164P/324P/644PV – 2.7V - 5.5V for ATmega164P/324P/644P • Speed Grades – ATmega164P/324P/644PV MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega164P/324P/644P MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Power Consumption at 1 MHz, 1.8V, 25°C for ATmega164P/324P/644PV – Active: 0.4 mA – ...
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... Pin Configurations 1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF Figure 1-1. Note: 8011O–AVR–07/10 Pinout ATmega164P/324P/644P (PCINT8/XCK0/T0) PB0 (PCINT9/CLKO/T1) PB1 (PCINT10/INT2/AIN0) PB2 (PCINT11/OC0A/AIN1) PB3 (PCINT12/OC0B/SS) PB4 (PCINT13/MOSI) PB5 (PCINT14/MISO) PB6 (PCINT15/SCK) PB7 RESET VCC GND XTAL2 XTAL1 (PCINT24/RXD0) PD0 (PCINT25/TXD0) PD1 (PCINT26/RXD1/INT0) PD2 (PCINT27/TXD1/INT1) PD3 ...
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... Pinout - DRQFN Figure 1- Table 1- 8011O–AVR–07/10 DRQFN - Pinout ATmega164P Top view B1 B15 B2 B14 B3 B13 B4 B12 B5 B11 DRQFN - Pinout ATmega164P/324P PB5 A7 PD3 PB6 B6 PD4 PB7 A8 PD5 RESET B7 PD6 VCC A9 PD7 GND B8 VCC XTAL2 A10 GND XTAL1 B9 PC0 PD0 A11 PC1 ...
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... Overview The ATmega164P/324P/644P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega164P/324P/644P achieves throughputs approaching 1 MIPS per MHz allowing the sys- tem designer to optimize power consumption versus processing speed. 2.1 Block Diagram Figure 2-1 ...
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... Atmel ATmega164P/324P/644P is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The ATmega164P/324P/644P AVR is supported with a full suite of program and system devel- opment tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. ...
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... As inputs, Port A pins that are externally pulled low will source current if the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes active, even if the clock is not running. Port A also serves the functions of various special features of the ATmega164P/324P/644P as listed on 2.3.4 Port B (PB7:PB0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit) ...
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... through a low-pass filter. CC 2.3.11 AREF This is the analog reference pin for the Analog-to-digital Converter. 8011O–AVR–07/10 ATmega164P/324P/644P 331. Shorter pulses are not guaranteed to generate a reset. , even if the ADC is not used. If the ADC is used, it should be connected CC ”System and Reset 7 ...
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... I/O. Typically "LDS" and "STS" combined with "SBRS", "SBRC", "SBR", and "CBR". 3.3 Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. 8011O–AVR–07/10 ATmega164P/324P/644P 8 ...
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... This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- 8011O–AVR–07/10 Block Diagram of the AVR Architecture Program Flash Counter Program Memory Instruction Register Instruction Decoder Control Lines ATmega164P/324P/644P Data Bus 8-bit Status and Control Interrupt Unit General Purpose SPI Registrers Unit Watchdog ...
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... SPI, and other I/O functions. The I/O Memory can be accessed directly the Data Space locations following those of the Register File, 0x20 - 0x5F. In addition, the ATmega164P/324P/644P has Extended I/O space from 0x60 - 0xFF in SRAM where only the ST/STS/STD and LD/LDS/LDD instructions can be used. ...
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... The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. 8011O–AVR–07/10 ATmega164P/324P/644P ...
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... R15 Working R16 Registers R17 … R26 R27 R28 R29 R30 R31 Figure 4-2, each register is also assigned a data memory address, mapping them ATmega164P/324P/644P 0 Addr. 0x00 0x01 0x02 0x0D 0x0E 0x0F 0x10 0x11 0x1A X-register Low Byte 0x1B X-register High Byte ...
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... Data is pushed onto the stack Decremented by 2 Return address is pushed onto the stack with a subroutine call or interrupt Incremented by 1 Data is popped from the stack Incremented by 2 Return address is popped from the stack with return from subroutine or return from interrupt ATmega164P/324P/644P Figure 4- R26 (0x1A ...
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... SP7 SP6 SP5 R/W R/W R Initial values respectively for the ATmega164P/324P/644P. Stack Pointer size Device ATmega164P ATmega324P ATmega644P RAMPZ7 RAMPZ6 RAMPZ5 R/W R/W R The Z-pointer used by ELPM and SPM 7 0 RAMPZ directly generated from the selected clock source for the ...
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... Register File single clock cycle an ALU Single Cycle ALU Operation T1 clk CPU Total Execution Time Result Write Back for details. ”Memory Programming” on page ATmega164P/324P/644P ”Memory Program- ”Interrupts” on page 61. The list also ”Interrupts” on page 61 for more information ...
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... SREG = cSREG; /* restore SREG value (I-bit) */ When using the SEI instruction to enable interrupts, the instruction following SEI will be exe- cuted before any pending interrupts, as shown in this example. 8011O–AVR–07/10 ; store SREG value ; disable interrupts during timed sequence ; start EEPROM write ; restore SREG value (I-bit) ATmega164P/324P/644P 16 ...
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... A return from an interrupt handling routine takes five clock cycles. During these five clock cycles, the Program Counter (three bytes) is popped back from the Stack, the Stack Pointer is incre- mented by three, and the I-bit in SREG is set. 8011O–AVR–07/10 ; set Global Interrupt Enable ATmega164P/324P/644P 17 ...
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... AVR Memories 5.1 Overview This section describes the different memories in the ATmega164P/324P/644P. The AVR archi- tecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega164P/324P/644P features an EEPROM Memory for data storage. All three memory spaces are linear and regular. ...
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... SRAM Data Memory Figure 5-2 The ATmega164P/324P/644P is a complex microcontroller with more peripheral units than can be supported within the 64 location reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space from $060 - $FF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used ...
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... The 32 general purpose working registers, 64 I/O registers, 160 Extended I/O Registers and the 1024/2048/4096 bytes of internal data SRAM in the ATmega164P/324P/644P are all accessible through all these addressing modes. The Register File is described in ter File” on page Figure 5-2. 5.3.1 Data Memory Access Times This section describes the general access timing concepts for internal memory access ...
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... EEPROM Data Memory The ATmega164P/324P/644P contains 512B/1K/2K bytes of data EEPROM memory orga- nized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and the EEPROM Control Register ...
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... The I/O space definition of the ATmega164P/324P/644P is shown in page 413. All ATmega164P/324P/644P I/Os and peripherals are placed in the I/O space. All I/O locations may be accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32 general purpose working registers and the I/O space. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions ...
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... Initial Value • Bits 15:12 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bits 11:0 – EEAR8:0: EEPROM Address The EEPROM Address Registers – EEARH and EEARL specify the EEPROM address in the 4K bytes EEPROM space ...
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... EEPROM Mode Bits Programming EEPM0 Time Operation 0 3.4 ms Erase and Write in one operation (Atomic Operation) 1 1.8 ms Erase Only 0 1.8 ms Write Only 1 – Reserved for future use for details about Boot programming. ATmega164P/324P/644P ”Memory Pro- 24 ...
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... The calibrated Oscillator is used to time the EEPROM accesses. typical programming time for EEPROM access from the CPU. Table 5-2. Symbol EEPROM write (from CPU) 8011O–AVR–07/10 EEPROM Programming Time Number of Calibrated RC Oscillator Cycles 26,368 ATmega164P/324P/644P Table 5-2 on page 25 Typ Programming Time 3.3 ms lists the 25 ...
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... Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address and Data Registers */ EEAR = uiAddress; EEDR = ucData; /* Write logical one to EEMPE */ EECR |= (1<<EEMPE); /* Start eeprom write by setting EEPE */ EECR |= (1<<EEPE); 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 26 ...
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... Read data from Data Register in r16,EEDR ret (1) /* Wait for completion of previous write */ while(EECR & (1<<EEPE Set up address register */ EEAR = uiAddress; /* Start eeprom read by writing EERE */ EECR |= (1<<EERE); /* Return data from Data Register */ return EEDR; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 27 ...
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... R/W R/W R MSB R/W R/W R SRWn1 = SRW11 (upper sector) or SRW01 (lower sector), SRWn0 = SRW10 (upper sector) or SRW00 (lower sector). The ALE pulse in period T4 is only present if the next instruction accesses the RAM (internal or external). ATmega164P/324P/644P R/W R/W R/W R R/W R/W R/W ...
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... ASY Source clock System Clock Prescaler Clock Multiplexer Timer/Counter External Clock Oscillator Oscillator is halted, TWI address recognition in all sleep modes. I/O ATmega164P/324P/644P Flash and CPU Core RAM EEPROM ADC clk CPU clk FLASH Reset Logic Watchdog Timer Watchdog clock Watchdog ...
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... Device Clocking Options Select 1. For all fuses “1” means unprogrammed while “0” means programmed. to start oscillating and a minimum number of oscillating CC , the device issues an internal reset with a time-out delay (t CC ATmega164P/324P/644P (1) CKSEL3..0 1111 - 1000 0111 - 0110 0101 - 0100 ”On-chip Debug System” on page 46 ...
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... Figure 6-2. 8011O–AVR–07/10 Table 6-2. The frequency of the Watchdog Oscillator is voltage ”Typical Characteristics” on page Number of Watchdog Oscillator Cycles = 5.0V) Typ Time-out ( 4 Crystal Oscillator Connections C2 C1 ATmega164P/324P/644P 338. = 3.0V) Number of Cycles 4.3 ms 512 (8,192) Figure 6-2 on page XTAL2 XTAL1 GND 0 31 ...
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... This option should not be used with crystals, only with ceramic resonators. Start-up Times for the Low Power Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega164P/324P/644P ”Clock Source Connections” on page (1) Recommended Range for Capacitors C1 (2) and C2 (pF) (3) – 101 ...
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... Fuse can be programmed in order to divide the internal frequency must be ensured that the resulting divided clock meets the frequency specification of the device. Start-up Times for the Full Swing Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save 258 CK 258 ATmega164P/324P/644P Additional Delay from Reset (V = 5.0V) CKSEL0 CC 14CK 14CK + 4.1 ms 14CK + ...
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... The Low-frequency Crystal Oscillator is optimized for use with a 32.768 kHz watch crystal. When selecting crystals, load capasitance and crystal’s Equivalent Series Resistance, ESR must be taken into consideration. Both values are specified by the crystal vendor. ATmega164P/324P/644P oscillator is optimized for very low power consumption, and thus when selecting crystals, see 12.5 pF crystals Table 6-7 ...
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... Start-up Times for the Low Frequency Crystal Oscillator Clock Selection Start-up Time from Power-down and Power-save Reserved 32K CK 32K CK 32K CK Reserved 1. These options should only be used if frequency stability at start-up is not important for the application. ATmega164P/324P/644P ⋅ – s Additional Delay from Reset (V = 5.0V) CKSEL0 CC (1) ...
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... Start-up times for the Internal Calibrated RC Oscillator clock selection Start-up Time from Power- down and Power-save Reserved The device is shipped with this option selected. 1. ATmega164P/324P/644P and page 380 for more details. ”System Clock Prescaler” on ”OSCCAL – Oscillator Calibration Register” on Table 25-4 on page 296. CKSEL3..0 ...
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... Start-up Times for the 128 kHz Internal Oscillator Start-up Time from Power- down and Power-save Reserved External Clock Drive Configuration NC EXTERNAL CLOCK SIGNAL Crystal Oscillator Clock Frequency Nominal Frequency MHz ATmega164P/324P/644P Table 6-12. (2) CKSEL3..0 0011 Additional Delay from Reset 14CK 14CK + 4 ms 14CK + 64 ms XTAL2 XTAL1 GND CKSEL3..0 0000 SUT1 ...
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... System Clock Prescaler The ATmega164P/324P/644P has a system clock prescaler, and the system clock can be divided by setting the to decrease the system clock frequency and the power consumption when the requirement for processing power is low. This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals ...
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... Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in CLKPR to zero. 2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE. Interrupts must be disabled when changing prescaler setting to make sure the write procedure is not interrupted. 8011O–AVR–07/10 ATmega164P/324P/644P 39 ...
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... R/W R/W R/W Device Specific Calibration Value Table 25-4 on page 330. The application software can write this register to change 330. Calibration outside that range is not guaranteed CLKPCE – – R 41. ATmega164P/324P/644P CAL3 CAL2 CAL1 R/W R/W R – CLKPS3 CLKPS2 CLKPS1 R R/W ...
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... The device is shipped with the CKDIV8 Fuse programmed. Table 6-16. CLKPS3 8011O–AVR–07/10 Clock Prescaler Select CLKPS2 CLKPS1 ATmega164P/324P/644P CLKPS0 Clock Division Factor 128 0 256 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 0 Reserved 1 Reserved 41 ...
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... SRAM are unaltered when the device wakes up from sleep reset occurs during sleep mode, the MCU wakes up and executes from the Reset Vector. 8011O–AVR–07/10 for more details. presents the different clock systems in the ATmega164P/324P/644P, and Active Clock Domains and Wake-up Sources in the Different Sleep Modes. Active Clock Domains X ...
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... SPM/EEPROM ready interrupt, an external level interrupt on INT7 pin change interrupt can wakeup the MCU from ADC Noise Reduction mode. 8011O–AVR–07/10 ATmega164P/324P/644P level has dropped during the sleep period. CC 48. Writing this bit to one turns off the BOD in rele- 48 ...
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... SLEEP instruction makes the MCU enter Extended Standby mode. This mode is identical to Power-save mode with the exception that the Oscillator is kept running. From Extended Standby mode, the device wakes up in six clock cycles. 8011O–AVR–07/10 ATmega164P/324P/644P ”External Interrupts” on page 67 ”Clock Sources” on page 30. ...
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... If the reference is kept on in sleep mode, the output can be used immediately. Refer to age Reference” on page 54 8011O–AVR–07/10 ATmega164P/324P/644P ”PRR – Power Reduction Register” on page ”AC - Analog Comparator” on page 237 for details on the start-up time. ...
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... Input Enable and Sleep Modes” on page 76 /2, the input buffer will use excessive power input pin can cause significant current even in active mode. Digital CC ”DIDR1 – Digital Input Disable Register 1” on page 239 for details. ATmega164P/324P/644P and ”DIDR0 – Digital for details on 46 ...
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... Sleep Mode Select SM1 SM0 Standby modes are only recommended for use with external crystals or resonators. ATmega164P/324P/644P – SM2 SM1 SM0 R R/W R/W R Table 7-2. Sleep Mode Idle ADC Noise Reduction Power-down Power-save Reserved Reserved (1) Standby (1) Extended Standby 0 SE SMCR R/W ...
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... JTD BODS BODSE R 42. Writing to the BODS bit is controlled by a timed sequence and an enable bit PRTWI PRTIM2 PRTIM0 PRUSART1 R/W R/W R/W R ATmega164P/324P/644P PUD – – IVSEL R R PRTIM1 PRSPI PRUSART0 R/W R/W R ...
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... Bit 0 - PRADC: Power Reduction ADC Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down. The analog comparator cannot use the ADC input MUX when the ADC is shut down. 8011O–AVR–07/10 ATmega164P/324P/644P 49 ...
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... Reset Sources The ATmega164P/324P/644P has five sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is present on the RESET pin for longer than the minimum pulse length. • ...
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... Watchdog Oscillator Clock Generator CKSEL[3:0] SUT[1:0] ”System and Reset Characteristics” on page rise. The RESET signal is activated again, without any delay, CC decreases below the detection level. CC ATmega164P/324P/644P DATA BUS MCU Status Register (MCUSR) Delay Counters CK TIMEOUT 331. The POR is activated whenever 51 ...
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... CC V RST RESET t TOUT RESET MCU Start-up, RESET Extended Externally V POT V CC RESET RESET ”System and Reset Characteristics” on page External Reset During Operation CC ATmega164P/324P/644P CC V RST t TOUT 331) will generate a – on its positive edge, the RST – has expired. TOUT 52 ...
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... Brown-out Detection ATmega164P/324P/644P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V level during operation by comparing fixed trigger level. The trigger level for the BOD CC can be selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detection level should be interpreted as V ...
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... Internal Voltage Reference ATmega164P/324P/644P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 8.7.1 Voltage Reference Enable Signals and Start-up Time The voltage reference has a start-up time that may influence the way it should be used. The start-up time is given in reference is not always turned on ...
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... Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode 8.8.2 Overview ATmega164P/324P/644P has an Enhanced Watchdog Timer (WDT). The WDT is a timer count- ing cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out value. In normal operation mode required that the system uses the WDR - Watchdog Timer Reset - instruction to restart the counter before the time-out value is reached ...
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... Clear WDRF in MCUSR */ MCUSR &= ~(1<<WDRF); /* Write logical one to WDCE and WDE */ /* Keep old prescaler setting to prevent unintentional time-out */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Turn off WDT */ WDTCSR = 0x00; __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega164P/324P/644P 56 ...
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... Turn on global interrupt sei ret (1) __disable_interrupt(); __watchdog_reset(); /* Start timed equence */ WDTCSR |= (1<<WDCE) | (1<<WDE); /* Set new prescaler(time-out) value = 64K cycles (~0 WDTCSR = (1<<WDE) | (1<<WDP2) | (1<<WDP0); __enable_interrupt(); 1. The example code assumes that the part specific header file is included. ATmega164P/324P/644P 57 ...
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... To make use of the Reset Flags to identify a reset condition, the user should read and then Reset the MCUSR as early as possible in the program. If the register is cleared before another reset occurs, the source of the reset can be found by examining the Reset Flags. 8011O–AVR–07/10 ATmega164P/324P/644P – ...
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... Watchdog Timer Configuration WDE WDIE Mode 0 0 Stopped 0 1 Interrupt Mode 1 0 System Reset Mode Interrupt and System Reset 1 1 Mode x x System Reset Mode ATmega164P/324P/644P WDE WDP2 WDP1 WDP0 R/W R/W R/W R Action on Time-out None Interrupt Reset Interrupt, then go to System ...
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... WDP1 WDP0 16K (16384) cycles 32K (32768) cycles 64K (65536) cycles 128K (131072) cycles 256K (262144) cycles 512K (524288) cycles 1024K (1048576) cycles ATmega164P/324P/644P Typical Time-out at Cycles (2048) cycles 4K (4096) cycles 8K (8192) cycles Reserved = 5. 0.125s 0.25s 0.5s 1.0s 2.0s 4.0s 8.0s 60 ...
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... Interrupts 9.1 Overview ATmega164P/324P/644P. For a general explanation of the AVR interrupt handling, refer to ”Reset and Interrupt Handling” on page 9.2 Interrupt Vectors in ATmega164P/324P/644P Table 9-1. Vector No 8011O–AVR–07/10 15. Reset and Interrupt Vectors Program (2) Address Source (1) $0000 RESET $0002 INT0 $0004 INT1 ...
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... Reset Vector is in the Application section while the Interrupt Vectors are in the Boot section or vice versa. Table 9-2. BOOTRST Note: The most typical and general program setup for the Reset and Interrupt Vector Addresses in ATmega164P/324P/644P is: Address 0x0000 0x0002 0x0004 0x0006 ...
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... When the BOOTRST Fuse is programmed and the Boot section size set to 8 Kbytes, the most typical and general program setup for the Reset and Interrupt Vector Addresses is: Address Labels Code .org 0x0002 0x00002 8011O–AVR–07/10 ATmega164P/324P/644P jmp TIM0_COMPB jmp TIM0_OVF jmp ...
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... RESET: ldi 0x1F03F 0x1F040 0x1F041 0x1F042 0x1FO43 9.2.1 Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table. 8011O–AVR–07/10 ATmega164P/324P/644P jmp EXT_INT1 ; IRQ1 Handler ... ... ; jmp SPM_RDY ; SPM Ready Handler r16,high(RAMEND) ...
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... Application section. If Interrupt Vectors are placed in the Application section and Boot Lock bit BLB12 is programed, interrupts are disabled while executing from the Boot Loader section. Refer to the section for details on Boot Lock bits. ATmega164P/324P/644P ...
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... MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret /* GET MCUCR*/ temp = MCUCR; /* Enable change of Interrupt Vectors */ MCUCR = temp|(1<<IVCE); /* Move interrupts to Boot Flash section */ MCUCR = temp|(1<<IVSEL); ATmega164P/324P/644P 66 ...
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... Initial Value • Bits 7:6 – Reserved These bits are reserved in the ATmega164P/324P/644P, and will always read as zero. • Bits 5:0 – ISC21, ISC20 – ISC00, ISC00: External Interrupt Sense Control Bits The External Interrupts are activated by the external pins INT2:0 if the SREG I-flag and the corresponding interrupt mask in the EIMSK is set ...
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... When changing the ISCn1/ISCn0 bits, the interrupt must be disabled by clearing its Interrupt Enable bit in the EIMSK Register. Otherwise an interrupt can occur when the bits are changed – – – – – – R for more information. ATmega164P/324P/644P – – INT2 INT1 R R R/W R – – INTF2 INTF1 R R ...
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... If the I-bit in SREG and the PCIE2 bit in EIMSK are set (one), the MCU will jump to the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alter- natively, the flag can be cleared by writing a logical one to it. 8011O–AVR–07/10 ATmega164P/324P/644P – ...
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... PCINT30 PCINT29 PCINT28 R/W R/W R/W R PCINT23 PCINT22 PCINT21 PCINT20 R/W R/W R/W R PCINT15 PCINT14 PCINT13 PCINT12 R/W R/W R/W R ATmega164P/324P/644P PCINT27 PCINT26 PCINT25 PCINT24 R/W R/W R/W R PCINT19 PCINT18 PCINT17 PCINT16 R/W R/W R/W R PCINT11 PCINT10 PCINT9 PCINT8 R/W R/W ...
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... If PCINT7:0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on the cor- responding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding I/O pin is disabled. 8011O–AVR–07/ PCINT7 PCINT6 PCINT5 PCINT4 R/W R/W R/W R ATmega164P/324P/644P PCINT3 PCINT2 PCINT1 PCINT0 R/W R/W R/W R PCMSK0 71 ...
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... Ground as indicated in CC for a complete list of parameters. Pxn C pin ”Register Description” on page 78. Refer to the individual module sections for a full description of the alter- ATmega164P/324P/644P Figure 11-1. Refer to ”Electrical Char Logic See Figure "General Digital I/O" for Details 91. ” ...
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... I/O CLOCK I/O 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. 91, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits ATmega164P/324P/644P Figure 11-2 PUD Q D ...
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... Input 1 1 Input 0 X Output 1 X Output Figure 11-2, the PINxn Register bit and the preceding latch con- pd,max ATmega164P/324P/644P Pull-up Comment No Tri-state (Hi-Z) Yes Pxn will source current if ext. pulled low. No Tri-state (Hi-Z) No Output Low (Sink) No Output High (Source) Figure 11-3 ...
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... SYNC LATCH PINxn r17 Figure 11-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of SYSTEM CLK r16 out PORTx, r16 SYNC LATCH PINxn r17 ATmega164P/324P/644P XXX in r17, PINx 0x00 t pd, max t pd, min 0xFF nop in r17, PINx ...
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... Figure 11-2, the digital input signal can be clamped to ground at the input of the ”Alternate Port Functions” on page ATmega164P/324P/644P /2. CC 78. 76 ...
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... In this case, the pull-up will be disabled during reset. If low power consumption during reset is important recommended to use an external pull-up or pull-down. Connecting unused pins directly to V accidentally configured as an output. 8011O–AVR–07/10 or GND is not recommended, since this may cause excessive currents if the pin is CC ATmega164P/324P/644P 77 ...
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... Pxn, PORT TOGGLE OVERRIDE ENABLE 1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk SLEEP, and PUD are common to all ports. All other signals are unique for each pin. ATmega164P/324P/644P Figure 11-2 on page 73 PUD ...
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... Unless the Digital Input is used as a clock source, the module with the alternate function will use its own synchronizer. This is the Analog Input/output to/from alternate functions. The Analog signal is connected directly to the pad, and can be used bi- Input/Output directionally. ATmega164P/324P/644P Fig- 79 ...
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... ADC4 (ADC input channel 4) PCINT4 (Pin Change Interrupt 4) ADC3 (ADC input channel 3) PCINT3 (Pin Change Interrupt 3) ADC2 (ADC input channel 2) PCINT2 (Pin Change Interrupt 2) ADC1 (ADC input channel 1) PCINT1 (Pin Change Interrupt 1) ADC0 (ADC input channel 0) PCINT0 (Pin Change Interrupt 0) ATmega164P/324P/644P Table 11- ...
Page 81
... PCINT3 • PCIE0 + PCINT2 • PCIE0 + ADC3D ADC2D PCINT3 • PCIE0 PCINT2 • PCIE0 PCINT3 INPUT PCINT2 INPUT ADC3 INPUT ADC2 INPUT ATmega164P/324P/644P relates the alternate functions of Port A to the 78. PA5/ADC5/ PA4/ADC4/ PCINT5 PCINT4 PCINT5 • PCIE0 + PCINT4 • PCIE0 + ADC5D ADC4D PCINT5 • ...
Page 82
... AIN0 (Analog Comparator Positive Input) INT2 (External Interrupt 2 Input) PCINT10 (Pin Change Interrupt 10) T1 (Timer/Counter 1 External Counter Input) CLKO (Divided System Clock Output) PCINT9 (Pin Change Interrupt 9) T0 (Timer/Counter 0 External Counter Input) XCK0 (USART0 External Clock Input/Output) PCINT8 (Pin Change Interrupt 8) ATmega164P/324P/644P Table 11-6. 82 ...
Page 83
... CLKO, Divided System Clock: The divided system clock can be output on the PB1 pin. The divided system clock will be output if the CKOUT Fuse is programmed, regardless of the PORTB1 and DDB1 settings. It will also be output during reset. PCINT9, Pin Change Interrupt source 9: The PB1 pin can serve as an external interrupt source. 8011O–AVR–07/10 ATmega164P/324P/644P 83 ...
Page 84
... INT2 ENABLE PCINT11 • PCIE1 PCINT10 • PCIE1 1 1 INT2 INPUT PCINT11 INPUT PCINT10 INPUT AIN1 INPUT AIN0 INPUT ATmega164P/324P/644P PB5/MOSI/ PB4/SS/OC0B/ PCINT13 PCINT12 SPE • MSTR SPE • MSTR PORTB13 • PUD PORTB12 • PUD SPE • MSTR SPE • MSTR ...
Page 85
... TMS (JTAG Test Mode Select) PCINT19 (Pin Change Interrupt 19) TCK (JTAG Test Clock) PCINT18 (Pin Change Interrupt 18) SDA (2-wire Serial Bus Data Input/Output Line) PCINT17 (Pin Change Interrupt 17) SCL (2-wire Serial Bus Clock Line) PCINT16 (Pin Change Interrupt 16) ATmega164P/324P/644P Table 11-9. 85 ...
Page 86
... AS2 • EXCLK AS2 AS2 • EXCLK + AS2 + PCINT23 • PCIE2 PCINT22 • PCIE2 AS2 EXCLK + AS2 PCINT23 INPUT PCINT22 INPUT T/C2 OSC T/C2 OSC OUTPUT INPUT ATmega164P/324P/644P PC5/TDI/ PC4/TDO/ PCINT21 PCINT20 JTAGEN JTAGEN 1 1 JTAGEN JTAGEN SHIFT_IR + 0 SHIFT_DR 0 JTAGEN 0 TDO JTAGEN + JTAGEN + PCINT21 • ...
Page 87
... PCINT27 (Pin Change Interrupt 27) INT0 (External Interrupt0 Input) RXD1 (USART1 Receive Pin) PCINT26 (Pin Change Interrupt 26) TXD0 (USART0 Transmit Pin) PCINT25 (Pin Change Interrupt 25) RXD0 (USART0 Receive Pin) PCINT24 (Pin Change Interrupt 24) ATmega164P/324P/644P PC1/SDA/ PC0/SCL/ PCINT17 PCINT16 TWEN TWEN PORTC1 • PUD PORTC0 • ...
Page 88
... TXD1, Transmit Data (Data output pin for the USART1). When the USART1 Transmitter is enabled, this pin is configured as an output regardless of the value of DDD3. PCINT27, Pin Change Interrupt Source 27: The PD3 pin can serve as an external interrupt source. 8011O–AVR–07/10 ATmega164P/324P/644P 88 ...
Page 89
... Table 11-13 on page 89 the overriding signals shown in Table 11-13. Overriding Signals for Alternate Functions PD7:PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8011O–AVR–07/10 ATmega164P/324P/644P and Table 11-14 on page 90 Figure 11-5 on page 78. PD6/ICP1/ PD7/OC2A/ OC2B/ PCINT31 PCINT30 ...
Page 90
... When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0 and PD1. This is not shown in this table. In addition, spike filters are connected between the AIO outputs shown in the port figure and the digital logic of the TWI module. ATmega164P/324P/644P (1) PD1/TXD0/ ...
Page 91
... PORTB4 R/W R/W R/W R DDB7 DDB6 DDB5 DDB4 R/W R/W R/W R PINB7 PINB6 PINB5 PINB4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega164P/324P/644P – – IVSEL IVCE R R R/W R PORTA3 PORTA2 PORTA1 PORTA0 R/W R/W R/W R DDA3 DDA2 DDA1 DDA0 ...
Page 92
... R/W R/W R/W R DDD7 DDD6 DDD5 DDD4 R/W R/W R/W R PIND7 PIND6 PIND5 PIND4 R/W R/W R/W R/W N/A N/A N/A N/A ATmega164P/324P/644P PORTC3 PORTC2 PORTC1 PORTC0 R/W R/W R/W R DDC3 DDC2 DDC1 DDC0 R/W R/W R/W R PINC3 PINC2 PINC1 PINC0 ...
Page 93
... Mask Register (TIMSK0). TIFR0 and TIMSK0 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler external clock source on the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter 8011O–AVR–07/10 ATmega164P/324P/644P ”Pin Configurations” on page ”Register Description” on page 104. ...
Page 94
... The TOP value can be assigned to be the fixed value 0xFF (MAX) or the value stored in the OCR0A Register. The assignment is depen- dent on the mode of operation. ”Timer/Counter Prescaler” on page DATA BUS count clear TCNTn direction bottom ATmega164P/324P/644P 152. TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ...
Page 95
... Signalize that TCNT0 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T0 98. shows a block diagram of the Output Compare unit. ATmega164P/324P/644P in the following. T0 (”Modes of Operation” on page 98). ”Modes of 95 ...
Page 96
... Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0 equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform 8011O–AVR–07/10 DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega164P/324P/644P TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 96 ...
Page 97
... The design of the Output Compare pin logic allows initialization of the OC0x state before the out- put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of operation. 8011O–AVR–07/10 COMnx1 Waveform COMnx0 Generator FOCn clk I/O See Section “12.9” on page 104. ATmega164P/324P/644P Figure 12-4 shows a simplified OCnx OCnx PORT ...
Page 98
... Compare Match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. 8011O–AVR–07/10 Table 12-2 on page 104, and for phase correct PWM refer to 122.). ”Timer/Counter Timing Diagrams” on page ATmega164P/324P/644P 104. For fast PWM mode, refer to Table 12-4 on page 105. 102. Figure 12-5. The counter value (TCNT0) ...
Page 99
... In fast PWM mode, the counter is incremented until the counter value matches the TOP value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast 8011O–AVR–07/10 ATmega164P/324P/644P ...
Page 100
... A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set- ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform generated will have a maximum frequency of f 8011O–AVR–07/10 ATmega164P/324P/644P Figure 12-6. The TCNT0 value is in the timing diagram shown as a his- 1 ...
Page 101
... OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to 8011O–AVR–07/10 12-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating 1 ATmega164P/324P/644P OCnx Interrupt Flag Set OCRnx Update TOVn Interrupt Flag Set (COMnx1 ...
Page 102
... Figure 12-8 contains timing data for basic Timer/Counter operation. The figure I/O Tn /1) I/O MAX - 1 shows the same timing data, but with the prescaler enabled. ATmega164P/324P/644P 105). The actual OC0x value will only f clk_I/O = ----------------- - ⋅ N 510 OCnx has a transition from high to low even though Figure 12-7 ...
Page 103
... OCF0B in all modes and OCF0A in all modes except CTC I/O Tn /8) I/O OCRnx - 1 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast caler (f /8) clk_I/O I/O Tn /8) I/O TOP - 1 ATmega164P/324P/644P /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP BOTTOM + 1 /8) clk_I/O OCRnx + 2 ...
Page 104
... A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at BOTTOM. See page 99 for more details. shows the COM0A1:0 bit functionality when the WGM02:0 bits are set ATmega164P/324P/644P COM0B0 – ...
Page 105
... A special case occurs when OCR0B equals TOP and COM0B1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done atBOTTOM. See 99 for more details. ATmega164P/324P/644P (1) ”Phase Correct PWM Mode” on shows the COM0A1:0 bit functionality when the (1) ” ...
Page 106
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bits 1:0 – WGM01:0: Waveform Generation Mode Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting ...
Page 107
... These bits are reserved bits and will always read as zero. • Bit 3 – WGM02: Waveform Generation Mode See the description in the 8011O–AVR–07/ FOC0A FOC0B – – ”TCCR0A – Timer/Counter Control Register A” on page ATmega164P/324P/644P WGM02 CS02 CS01 CS00 R/W R/W R/W R 104. TCCR0B 107 ...
Page 108
... I clk /1024 (From prescaler) I External clock source on T0 pin. Clock on falling edge External clock source on T0 pin. Clock on rising edge R/W R/W R/W R R/W R/W R/W R ATmega164P/324P/644P TCNT0[7:0] R/W R/W R OCR0A[7:0] R/W R/W R TCNT0 R OCR0A R/W 0 108 ...
Page 109
... Flag Register – TIFR0. 12.9.7 TIFR0 – Timer/Counter 0 Interrupt Flag Register Bit 0x15 (0x35) Read/Write Initial Value • Bits 7:3 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. 8011O–AVR–07/10 ATmega164P/324P/644P OCR0B[7:0] ...
Page 110
... When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed. The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Generation Mode Bit Description” on page 8011O–AVR–07/10 ATmega164P/324P/644P Table 106. 12-8, ”Waveform ...
Page 111
... I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 8011O–AVR–07/10 ATmega164P/324P/644P ”Pin Configurations” on page ”Register Description” on page 132. ”PRR – Power Reduction Register” on page 48 Figure 13-1 ...
Page 112
... Count Clear Control Logic Direction Timer/Counter TCNTn = OCRnA = OCRnB ICRn TCCRnA Refer to Figure 1-1 on page 2 and ”Alternate Port Functions” on page 78 placement and description. ATmega164P/324P/644P (Note:) TOVn (Int.Req.) Clock Select clk Tn Edge Detector TOP BOTTOM ( From Prescaler ) = = 0 OCnA (Int.Req.) Waveform ...
Page 113
... The counter reaches the TOP when it becomes equal to the highest value in the count sequence. The TOP value can be assigned to be one of the fixed values: 0x00FF, 0x01FF, or 0x03FF the value stored in the OCRnA or ICRn Register. The assignment is dependent of the mode of operation. ATmega164P/324P/644P (See 113 ...
Page 114
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega164P/324P/644P 114 ...
Page 115
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ATmega164P/324P/644P 115 ...
Page 116
... For I/O Registers located in extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI” instructions must be replaced with instructions that allow access to extended I/O. Typically “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. ”Timer/Counter Prescaler” on page ATmega164P/324P/644P 152. 116 ...
Page 117
... Signalize that TCNTn has reached minimum value (zero). ). The clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear ”Modes of Operation” on page ATmega164P/324P/644P TOVn (Int.Req.) Clock Select Edge Detector clk Tn Control Logic ( From Prescaler ) TOP BOTTOM 123 ...
Page 118
... ICRn Register for defining the counter’s TOP value. In these cases the Waveform Genera- 8011O–AVR–07/10 DATA BUS TEMP (8-bit) ICRnH (8-bit) ICRnL (8-bit) ICRn (16-bit Register) WRITE ACO* ACIC* Analog Comparator ICPn ATmega164P/324P/644P Figure 13-3. The elements of (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) ICNC ICES Noise Edge ICFn (Int.Req.) Canceler ...
Page 119
... Changing the edge sensing must be done as early as possible after the ICRn Register has been read. After a change of the edge, the Input Capture Flag (ICFn) must be 8011O–AVR–07/10 113. ATmega164P/324P/644P ”Accessing 16-bit Registers” (Figure 13-1 on page 112). The edge detector is also ...
Page 120
... Output Compare unit. The small “n” in the register and DATA BUS TEMP (8-bit) OCRnxH Buf. (8-bit) OCRnxL Buf. (8-bit) OCRnx Buffer (16-bit Register) OCRnxH (8-bit) OCRnxL (8-bit) OCRnx (16-bit Register) TOP BOTTOM ATmega164P/324P/644P 123.) (8-bit) TCNTnH (8-bit) TCNTnL (8-bit) TCNTn (16-bit Counter) = (16-bit Comparator ) OCFnx (Int.Req.) Waveform Generator WGMn3:0 ...
Page 121
... Normal mode. The OCnx Register keeps its value even when changing between Waveform Generation modes. Be aware that the COMnx1:0 bits are not double buffered together with the compare value. Changing the COMnx1:0 bits will take effect immediately. 8011O–AVR–07/10 113. ATmega164P/324P/644P ”Accessing 16-bit Registers” 121 ...
Page 122
... The design of the Output Compare pin logic allows initialization of the OCnx state before the out- put is enabled. Note that some COMnx1:0 bit settings are reserved for certain modes of operation. The COMnx1:0 bits have no effect on the Input Capture unit. 8011O–AVR–07/10 Waveform Generator I/O See Section “13.11” on page 132. ATmega164P/324P/644P Figure 13 OCnx ...
Page 123
... The OCRnA or ICRn define the top value for the counter, hence also its resolution. This mode allows greater control of the compare match output frequency. It also simplifies the opera- tion of counting external events. 8011O–AVR–07/10 ATmega164P/324P/644P Table 13-2 on page 132. For fast PWM mode refer to 122.) ” ...
Page 124
... PWM mode can be twice as high as the phase cor- 8011O–AVR–07/ when OCRnA is set to zero (0x0000). The waveform frequency clk_I -------------------------------------------------- - OCnA ⋅ ATmega164P/324P/644P Figure 13-6. The counter value (TCNTn) OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) (COMnA1 clk_I/O ⋅ OCRnA 1 + 124 ...
Page 125
... Note that when using fixed TOP values the unused bits are masked to zero when any of the OCRnx Registers are written. The procedure for updating ICRn differs from updating OCRnA when used for defining the TOP value. The ICRn Register is not double buffered. This means that if ICRn is changed to a low 8011O–AVR–07/10 ATmega164P/324P/644P ( TOP log R ...
Page 126
... TCNTn and OCRnx while upcounting, and set on the compare match while downcounting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation has lower maximum operation frequency than single slope 8011O–AVR–07/10 ATmega164P/324P/644P Table on page f clk_I/O ...
Page 127
... Compare Registers. If the TOP value is lower than any of the Compare Registers, a compare match will never occur between the TCNTn and the OCRnx. Note that when using fixed TOP values, the unused bits are masked to zero when any of the 8011O–AVR–07/10 ATmega164P/324P/644P ( ) TOP ...
Page 128
... Figure The PWM resolution for the phase and frequency correct PWM mode can be defined by either ICRn or OCRnA. The minimum resolution allowed is 2-bit (ICRn or OCRnA set to 0x0003), and 8011O–AVR–07/10 f OCnxPCPWM 13-9). ATmega164P/324P/644P Figure 13-8 illustrates, changing the Table on page f clk_I/O = --------------------------- - ⋅ ...
Page 129
... R = ---------------------------------- - PFCPWM Figure 13-9. The figure shows phase and frequency correct shows the output generated is, in contrast to the phase correct mode, symmetri- ATmega164P/324P/644P ( ) TOP log OCnA Interrupt Flag Set or ICFn Interrupt Flag Set (Interrupt on TOP) OCRnx/TOP Updateand TOVn Interrupt Flag Set ...
Page 130
... OCnxPFCPWM Figure 13-10 clk I/O clk Tn (clk /1) I/O TCNTn OCRnx - 1 OCRnx OCFnx shows the same timing data, but with the prescaler enabled. ATmega164P/324P/644P f clk_I/O = --------------------------- - ⋅ ⋅ TOP ) is therefore shown shows a timing diagram for the setting of OCFnx. OCRnx OCRnx + 1 OCRnx Value Table on ...
Page 131
... I/O TCNTn TOP - 1 TCNTn TOP - 1 TOVn (FPWM) (if used as TOP) OCRnx Old OCRnx Value (Update at TOP) shows the same timing data, but with the prescaler enabled. ATmega164P/324P/644P OCRnx OCRnx + 1 OCRnx Value TOP BOTTOM TOP TOP - 1 New OCRnx Value /8) clk_I/O OCRnx + 2 BOTTOM + 1 TOP - 2 ...
Page 132
... OCRnx Old OCRnx Value (Update at TOP COM1A1 COM1A0 COM1B1 R/W R/W R Table 13-2 on page 132 Compare Output Mode, non-PWM COMnA0/COMnB0 ATmega164P/324P/644P /8) clk_I/O TOP BOTTOM TOP TOP - 1 New OCRnx Value COM1B0 – – WGM11 R R shows the COMnx1:0 bit functionality Description Normal port operation, OCnA/OCnB disconnected. ...
Page 133
... A special case occurs when OCRnA/OCRnB equals TOP and COMnA1/COMnB1 is set. Section “13.9.4” on page 126. for more details. Table 13-5 on page ATmega164P/324P/644P (1) Description Normal port operation, OCnA/OCnB disconnected. WGMn3 15: Toggle OC1A on Compare Match, OC1B disconnected (normal port operation). For all other WGM1 settings, normal port operation, OC1A/OC1B disconnected ...
Page 134
... CTC 0 1 (Reserved Fast PWM 1 1 Fast PWM ICNC1 ICES1 – WGM13 R/W R ATmega164P/324P/644P Update of x TOP OCRn 0xFFFF Immediate 0x00FF TOP 0x01FF TOP 0x03FF TOP OCRnA Immediate 0x00FF BOTTOM 0x01FF BOTTOM 0x03FF BOTTOM ICRn BOTTOM OCRnA BOTTOM ICRn ...
Page 135
... I clk /256 (From prescaler) I clk /1024 (From prescaler) I External clock source on Tn pin. Clock on falling edge External clock source on Tn pin. Clock on rising edge FOC1A FOC1B – R/W R ATmega164P/324P/644P – – – – Figure 0 – TCCR1C R 0 135 ...
Page 136
... The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes are written simultaneously when the CPU writes to these registers, the access is performed using an 8-bit temporary High Byte Register (TEMP). This temporary register is shared by all the other 16-bit registers. 8011O–AVR–07/10 ATmega164P/324P/644P ...
Page 137
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector (see “ ...
Page 138
... Initial Value • Bit 7:6 – Res: Reserved Bits These bits are unused bits in the ATmega164P/324P/644P, and will always read as zero. • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register (ICR1) is set by the WGMn3 used as the TOP value, the ICF1 Flag is set when the coun- ter reaches the TOP value ...
Page 139
... BOTTOM Timer/Counter TCNTn = = OCRnA Fixed TOP Value = OCRnB Synchronized Status flags asynchronous mode Status flags ASSRn TCCRnA TCCRnB ATmega164P/324P/644P 2. CPU accessible I/O Registers, includ- 152. ”PRR – Power Reduction Register” on TOVn (Int.Req.) clk Tn T/C Oscillator Prescaler clk I OCnA (Int.Req.) Waveform ...
Page 140
... OCR2A Register. The assignment is depen- dent on the mode of operation default equal to the MCU clock, clk T2 152. ATmega164P/324P/644P for details. The compare match event will also set the 157. For details on clock sources and prescaler, see . When the AS2 I/O ” ...
Page 141
... Signalizes that TCNT2 has reached maximum value. Signalizes that TCNT2 has reached minimum value (zero). ). clk can be generated from an external or internal clock source present or not. A CPU write overrides (has priority over) all counter clear or T2 144. ATmega164P/324P/644P TOVn (Int.Req.) T/C clk Tn Oscillator Prescaler clk top in the following ...
Page 142
... TCNT2 without triggering an interrupt when the Timer/Counter clock is enabled. 8011O–AVR–07/10 shows a block diagram of the Output Compare unit. DATA BUS OCRnx = (8-bit Comparator ) top bottom Waveform Generator FOCn WGMn1:0 ATmega164P/324P/644P (”Modes of Operation” on page TCNTn OCFnx (Int.Req.) OCnx COMnX1:0 144). 142 ...
Page 143
... Generator if either of the COM2x1:0 bits are set. However, the OC2x pin direction (input or out- put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction 8011O–AVR–07/10 Waveform Generator clk I/O ATmega164P/324P/644P Figure 14-4 shows a simplified OCnx ...
Page 144
... This mode allows greater control of the compare match output frequency. It also simplifies the operation of counting external events. 8011O–AVR–07/10 ”Register Description” on page 152. Table 14-5 on page 154. For fast PWM mode, refer to Table 14-7 on page 143.). ”Timer/Counter Timing Diagrams” on page ATmega164P/324P/644P Table 14-6 on 154. 148. 144 ...
Page 145
... BOTTOM. Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice as high as the phase correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM mode well suited 8011O–AVR–07/10 ATmega164P/324P/644P Table 14-5 on page 1 2 ...
Page 146
... MAX+1 timer clock cycle. Setting the OCR2A equal to MAX will result in a constantly high or low output (depending on the polarity of the output set by the COM2A1:0 bits.) 8011O–AVR–07/10 ATmega164P/324P/644P Figure 14-6 on page 146. The TCNT2 value is in the timing diagram 1 ...
Page 147
... Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM value. 8011O–AVR–07/10 14-7. The TCNT2 value is in the timing diagram shown as a histogram for illustrating 1 ATmega164P/324P/644P = f /2 when OCR2A is set to zero. This fea- oc2 clk_I/O OCnx Interrupt Flag Set ...
Page 148
... Timer/Counter Oscillator clock. The figures include information on when Interrupt Flags are set. Figure 14-8 on page 149 shows the count sequence close to the MAX value in all modes other than phase correct PWM mode. 8011O–AVR–07/10 ATmega164P/324P/644P Table 14-4 on page f clk_I ...
Page 149
... I/O Tn /8) I/O MAX - 1 shows the setting of OCF2A in all modes except CTC mode. clk I/O clk Tn /8) I/O OCRnx - 1 ATmega164P/324P/644P MAX BOTTOM /8) clk_I/O MAX BOTTOM OCRnx OCRnx + 1 OCRnx Value BOTTOM + 1 BOTTOM + 1 /8) clk_I/O ...
Page 150
... OCR2x or TCNT2. If the write cycle is not finished, and the MCU enters sleep mode 8011O–AVR–07/10 shows the setting of OCF2A and the clearing of TCNT2 in CTC mode. caler (f /8) clk_I/O clk I/O clk Tn /8) I/O TOP - 1 Enable interrupts, if needed. ATmega164P/324P/644P TOP BOTTOM BOTTOM + 1 TOP 150 ...
Page 151
... Interrupt Flag. The Output Compare pin is changed on the timer clock and is not synchronized to the processor clock. 8011O–AVR–07/10 ) again becomes active, TCNT2 will read as the previous value (before entering sleep) ATmega164P/324P/644P 151 ...
Page 152
... By setting the AS2 bit in ASSR, Timer/Counter2 is asynchronously IO /256, and clk /1024. Additionally, clk T2S T2S COM2A1 COM2A0 COM2B1 R/W R/W R ATmega164P/324P/644P 10-BIT T/C PRESCALER 0 TIMER/COUNTER2 CLOCK SOURCE clk T2 . clk is by default connected to the main T2S T2S for details. /8, clk T2S as well as 0 (stop) may be selected. T2S ...
Page 153
... A special case occurs when OCR2A equals TOP and COM2A1 is set. In this case, the Com- pare Match is ignored, but the set or clear is done at TOP. See page 147 for more details. ATmega164P/324P/644P (1) ”Fast PWM Mode” on (1) ”Phase Correct PWM Mode” on ...
Page 154
... Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. 8011O–AVR–07/10 Table 14-5 shows the COM2B1:0 bit functionality when the WGM22:0 bits Compare Output Mode, non-PWM Mode COM2B0 Description 0 Normal port operation, OC2B disconnected ...
Page 155
... Reserved PWM, Phase Correct Reserved Fast PWM 1. MAX= 0xFF 2. BOTTOM= 0x00 FOC2A FOC2B – ATmega164P/324P/644P ”Modes of Operation” on page 144). Update of TOP OCRx at 0xFF Immediate 0xFF TOP OCRA Immediate 0xFF BOTTOM – – OCRA TOP – – OCRA BOTTOM – WGM22 ...
Page 156
... OCR2B as TOP. The FOC2B bit is always read as zero. • Bits 5:4 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bit 3 – WGM22: Waveform Generation Mode See the description in the • Bit 2:0 – CS22:0: Clock Select ...
Page 157
... A logical zero in this bit indicates that OCR2A is ready to be updated with a new value. 8011O–AVR–07/ OCR2A[7:0] R/W R/W R/W R OCR2B[7:0] R/W R/W R/W R – EXCLK AS2 TCN2UB OCR2AUB R R/W R ATmega164P/324P/644P R/W R/W R/W R R/W R/W R/W R OCR2BUB TCR2AUB TCR2BUB When AS2 is I/O OCR2A OCR2B 0 ASSR R 0 ...
Page 158
... When the TOIE2 bit is written to one and the I-bit in the Status Register is set (one), the Timer/Counter2 Overflow interrupt is enabled. The corresponding interrupt is executed if an overflow in Timer/Counter2 occurs, that is, when the TOV2 bit is set in the Timer/Counter2 Inter- rupt Flag Register – TIFR2. 8011O–AVR–07/10 ATmega164P/324P/644P – ...
Page 159
... TSM bit is set. Refer to the description of the “Bit 7 – TSM: Timer/Counter Syn- chronization Mode” on page 136 for a description of the Timer/Counter Synchronization mode. 8011O–AVR–07/ – – – – TSM – – – R ATmega164P/324P/644P – OCF2B OCF2A TOV2 R R/W R/W R – – PSRASY PSRSYNC R R R/W R TIFR2 GTCCR ...
Page 160
... When this bit is one, Timer/Counter1 and Timer/Counter0 prescaler will be Reset. This bit is nor- mally cleared immediately by hardware, except ifthe TSM bit is set. Note that Timer/Counter1 and Timer/Counter0 share the same prescaler and a reset of this prescaler will affect both timers. 8011O–AVR–07/10 ATmega164P/324P/644P 160 ...
Page 161
... Overview The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between the ATmega164P/324P/644P and peripheral devices or between several AVR devices. USART can also be used in Master SPI mode, see “USART in SPI Mode” on page 198. The Power Reduction SPI bit, PRSPI must be written to zero to enable SPI module ...
Page 162
... In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure correct sampling of the clock signal, the minimum low and high periods should be: Low period: longer than 2 CPU clock cycles. High period: longer than 2 CPU clock cycles. 8011O–AVR–07/10 ATmega164P/324P/644P Figure 15-2. The sys- SHIFT ENABLE ...
Page 163
... SPI Pin Overrides Direction, Master SPI User Defined Input User Defined User Defined 1. See ”Alternate Functions of Port B” on page 82 direction of the user defined SPI pins. ATmega164P/324P/644P ”Alternate Port Direction, Slave SPI Input User Defined Input Input for a detailed description of how to define the 163 ...
Page 164
... Set MOSI and SCK output, all others input */ DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK); /* Enable SPI, Master, set clock rate fck/16 */ SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0); /* Start transmission */ SPDR = cData; /* Wait for transmission complete */ while(!(SPSR & (1<<SPIF))) ; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 164 ...
Page 165
... Read received data and return r16,SPDR in ret (1) /* Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); /* Wait for reception complete */ while(!(SPSR & (1<<SPIF))) ; /* Return Data Register */ return SPDR; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 165 ...
Page 166
... SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing Table 15-2 on page 167 8011O–AVR–07/10 ATmega164P/324P/644P and Figure 15-4 on page 167. Data bits are shifted out and latched in on Table 15-3 on page 168 ...
Page 167
... SCK (CPOL = 1) mode 3 SAMPLE I MOSI/MISO CHANGE 0 MOSI PIN CHANGE 0 MISO PIN SS MSB first (DORD = 0) MSB Bit 6 LSB first (DORD = 1) LSB Bit 1 ATmega164P/324P/644P Leading Edge Sample (Rising) Setup (Rising) Sample (Falling) Setup (Falling) Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 ...
Page 168
... Figure 15-3 and Figure 15-4 CPOL Functionality CPOL Leading Edge 0 Rising 1 Falling Figure 15-3 CPHA Functionality CPHA Leading Edge 0 Sample 1 Setup ATmega164P/324P/644P CPOL CPHA SPR1 SPR0 R/W R/W R/W R for an example. The CPOL functionality is sum- Trailing Edge Falling Rising and Figure 15-4 for an example ...
Page 169
... SPI Data Register. • Bit 5:1 – Res: Reserved Bits These bits are reserved bits in the ATmega164P/324P/644P and will always read as zero. • Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods ...
Page 170
... The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. Reading the regis- ter causes the Shift Register Receive buffer to be read. 8011O–AVR–07/10 ATmega164P/324P/644P ...
Page 171
... USART1 and USART0 The ATmega164P/324P/644P has two USART’s, USART0 and USART1. The functionality for all USART’s is described below, most register and bit references in this sec- tion are written in general form. A lower case “n” replaces the USART number. ...
Page 172
... UBRR[H:L] BAUD RATE GENERATOR UDR (Transmit) TRANSMIT SHIFT REGISTER RECEIVE SHIFT REGISTER UDR (Receive) UCSRA 1. See Figure 1-1 on page 2 and ”Alternate Port Functions” on page 78 placement. ATmega164P/324P/644P Clock Generator OSC SYNC LOGIC PIN XCK CONTROL Transmitter TX CONTROL PARITY GENERATOR PIN TxD ...
Page 173
... Clock output to XCK pin (Internal Signal). Used for synchronous master operation. XTAL pin frequency (System Clock). contains equations for calculating the baud rate (in bits per second) and 1. The baud rate is defined to be the transfer rate in bit per second (bps) Baud rate (in bits per second, bps) ATmega164P/324P/644P U2X / ...
Page 174
... Rate f OSC BAUD = ----------------------------------------- - ( 16 UBRRn f OSC BAUD = -------------------------------------- - ( 8 UBRRn f OSC BAUD = -------------------------------------- - ( 2 UBRRn System Oscillator clock frequency Contents of the UBRRHn and UBRRLn Registers, (0-4095) Figure 16-2 on page 173 for details. ATmega164P/324P/644P Equation for Calculating UBRR Value f OSC UBRRn ----------------------- - 1 = 16BAUD ) OSC UBRRn ------------------- - 1 = 8BAUD ) OSC UBRRn = ------------------- - 1 ...
Page 175
... It is therefore recommended to osc UCPOL = 1 XCK RxD / TxD UCPOL = 0 XCK RxD / TxD Figure 16-3 on page 175 illustrates the possible combinations of the frame formats. Bits inside ATmega164P/324P/644P f OSC < f ---------- - XCK 4 Sample Sample shows, when UCPOLn is zero the data will ...
Page 176
... No transfers on the communication line (RxDn or TxDn). An IDLE line must be high. ⊕ even n 1 – ⊕ odd n 1 – Parity bit using even parity even Parity bit using odd parity odd Data bit n of the character n ATmega164P/324P/644P FRAME 4 [5] [6] [7] [8] [P] Sp1 [Sp2] … ⊕ ⊕ ⊕ ⊕ ⊕ ...
Page 177
... UCSRnC,r16 ret (1) /* Set baud rate */ UBRRHn = (unsigned char)(baud>>8); UBRRLn = (unsigned char)baud; /* Enable receiver and transmitter */ UCSRnB = (1<<RXENn)|(1<<TXENn); /* Set frame format: 8data, 2stop bit */ UCSRnC = (1<<USBSn)|(3<<UCSZn0); 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 177 ...
Page 178
... UCSRnA,UDREn rjmp USART_Transmit ; Put data (r16) into buffer, sends the data out UDRn,r16 ret (1) /* Wait for empty transmit buffer */ while ( !( UCSRnA & (1<<UDREn Put data into buffer, sends the data */ UDRn = data; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 178 ...
Page 179
... Put data into buffer, sends the data */ UDRn = data; 1. These transmit functions are written to be general functions. They can be optimized if the con- tents of the UCSRnB is static. For example, only the TXB8 bit of the UCSRnB Register is used after initialization. 2. See “About Code Examples” on page 8. ATmega164P/324P/644P 179 ...
Page 180
... The following code example shows a simple USART receive function based on polling of the Receive Complete (RXCn) Flag. When using frames with less than eight bits the most significant bits of the data read from the UDRn will be masked to zero. The USART has to be initialized before the function can be used. 8011O–AVR–07/10 ATmega164P/324P/644P 180 ...
Page 181
... UCSRnA, RXCn rjmp USART_Receive ; Get and return received data from buffer in r16, UDRn ret (1) /* Wait for data to be received */ while ( !(UCSRnA & (1<<RXCn Get and return received data from buffer */ return UDRn; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 181 ...
Page 182
... UCSRnA; resh = UCSRnB; resl = UDRn error, return - status & (1<<FEn)|(1<<DORn)|(1<<UPEn) ) return -1; /* Filter the 9th bit, then return */ resh = (resh >> 1) & 0x01; return ((resh << resl); 1. See “About Code Examples” on page 8. ATmega164P/324P/644P 182 ...
Page 183
... Checker calculates the parity of the data bits in incoming frames and compares the result with the parity bit from the serial frame. The result of the check is stored in the receive buffer together 8011O–AVR–07/10 ”Parity Bit Calculation” on page 176 ATmega164P/324P/644P and ”Parity Checker” on page 183. ...
Page 184
... Note the 8011O–AVR–07/10 (1) sbis UCSRnA, RXCn ret in r16, UDRn rjmp USART_Flush (1) unsigned char dummy; while ( UCSRnA & (1<<RXCn) ) dummy = UDRn; 1. See “About Code Examples” on page 8. ATmega164P/324P/644P Figure 16-5 184 ...
Page 185
... Figure 16-7 on page 186 of the start bit of the next frame. 8011O–AVR–07/10 RxD IDLE RxD Sample (U2X = Sample (U2X = shows the sampling of the stop bit and the earliest possible beginning ATmega164P/324P/644P START Figure 16-6 shows the sampling of the data bits and BIT ...
Page 186
... Double Speed mode the ratio of the slowest incoming data rate that can be accepted in relation to the receiver baud rate the ratio of the fastest incoming data rate that can be fast accepted in relation to the receiver baud rate. and Table 16-3 on page 187 ATmega164P/324P/644P STOP 1 (A) ( ...
Page 187
... ATmega164P/324P/644P Recommended Max Max Total Error (%) Receiver Error (%) +6.67/-6.8 ±3.0 +5.79/-5.88 ±2.5 +5.11/-5.19 ±2.0 +4.58/-4.54 ±2.0 +4.14/-4.19 ±1.5 +3.78/-3.83 ±1.5 Recommended Max Max Total Error (%) Receiver Error (%) +5 ...
Page 188
... Do not use Read-Modify-Write instructions (SBI and CBI) to set or clear the MPCMn bit. The MPCMn bit shares the same I/O location as the TXCn Flag and this might accidentally be cleared when using SBI or CBI instructions. 8011O–AVR–07/10 ATmega164P/324P/644P 188 ...
Page 189
... TXCIEn bit). • Bit 5 – UDREn: USART Data Register Empty The UDREn Flag indicates if the transmit buffer (UDRn) is ready to receive new data. If UDREn is one, the buffer is empty, and therefore ready to be written. The UDREn Flag can generate a 8011O–AVR–07/10 ATmega164P/324P/644P ...
Page 190
... TXCIEn bit is written to one, the Global Interrupt Flag in SREG is written to one and the TXCn bit in UCSRnA is set. 8011O–AVR–07/10 ”Multi-processor Communication Mode” on page RXCIEn TXCIEn UDRIEn RXENn R/W R/W R/W R ATmega164P/324P/644P 187 TXENn UCSZn2 RXB8n TXB8n R/W R UCSRnB 190 ...
Page 191
... UMSELn1 UMSELn0 UPMn1 R/W R/W R UMSELn Bits Settings UMSELn0 See ”USART in SPI Mode” on page 198 operation ATmega164P/324P/644P UPMn0 USBSn UCSZn1 UCSZn0 R/W R/W R/W R Table 16-4.. Mode Asynchronous USART Synchronous USART (Reserved) (1) Master SPI (MSPIM) for full description of the Master SPI Mode (MSPIM) ...
Page 192
... UPMn Bits Settings UPMn1 UPMn0 USBS Bit Settings USBSn Stop Bit(s) 0 1-bit 1 2-bit UCSZn Bits Settings UCSZn1 ATmega164P/324P/644P Parity Mode Disabled Reserved Enabled, Even Parity Enabled, Odd Parity UCSZn0 Character Size 0 5-bit 1 6-bit 0 7-bit 1 8-bit 0 Reserved 1 Reserved 0 Reserved 1 9-bit 192 ...
Page 193
... Transmitted Data Changed (Output of TxDn Pin) Rising XCKn Edge Falling XCKn Edge – – – – UBRR[7: R/W R/W R/W R ATmega164P/324P/644P Received Data Sampled (Input on RxDn Pin) Falling XCKn Edge Rising XCKn Edge UBRR[11: R/W R/W R/W R/W R/W R/W R/W R UBRRHn UBRRLn 193 ...
Page 194
... Kbps 230.4 Kbps ATmega164P/324P/644P Table 16-9 to ”Asynchronous ⎞ Closest Match • – 100% ⎠ 2.0000 MHz osc U2Xn = 0 Error UBRR Error UBRR 0.0% 51 0.2% 103 0.0% 25 ...
Page 195
... Kbps 0.5 Mbps ATmega164P/324P/644P f = 7.3728 MHz osc U2Xn = 0 U2Xn = 1 Error UBRR Error UBRR 0.2% 191 0.0% 383 0.2% 95 0.0% 191 0.2% 47 0.0% 95 -0.8% 31 0. ...
Page 196
... Mbps 691.2 Kbps ATmega164P/324P/644P MHz f = 14.7456 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 575 0.0% 383 0.0% 287 0.0% 191 0.0% 143 0.0% 95 0. ...
Page 197
... Mbps 1.152 Mbps ATmega164P/324P/644P f = 20.0000 MHz osc U2Xn = 1 U2Xn = 0 Error UBRR Error 959 0.0% 520 0.0% 479 0.0% 259 0.2% 239 0.0% 129 0.2% 159 0. ...
Page 198
... The baud rate or UBRRn setting can therefore be calculated using the same equations, see Table 17-1. Operating Mode Synchronous Master mode 8011O–AVR–07/10 Table 17-1: Equations for Calculating Baud Rate Register Setting Equation for Calculating Baud (1) Rate f OSC BAUD = -------------------------------------- - ( 2 UBRRn ATmega164P/324P/644P Equation for Calculating UBRRn Value f OSC UBRRn = ------------------- - 2BAUD + – 198 ...
Page 199
... UCPOL=0 XCK Data setup (TXD) Data sample (RXD) XCK Data setup (TXD) Data sample (RXD) ATmega164P/324P/644P Leading Edge Trailing Edge Sample (Rising) Setup (Falling) Setup (Rising) Sample (Falling) Sample (Falling) Setup (Rising) Setup (Falling) Sample (Rising) UCPOL=1 XCK Data setup (TXD) ...
Page 200
... Contrary to the normal mode USART operation the UBRRn must then be written to the desired value after the transmitter is enabled, but before the first transmission is started. Setting UBRRn to zero before enabling the transmitter is not neces- sary if the initialization is done immediately after a reset since UBRRn is reset to zero. ATmega164P/324P/644P 200 ...