ATMEGA16-16AUR Atmel, ATMEGA16-16AUR Datasheet - Page 128
![MCU AVR 128KB FLASH 16MHZ 44TQFP](/photos/6/70/67042/313-44-tqfp_sml.jpg)
ATMEGA16-16AUR
Manufacturer Part Number
ATMEGA16-16AUR
Description
MCU AVR 128KB FLASH 16MHZ 44TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16L-8MI.pdf
(357 pages)
Specifications of ATMEGA16-16AUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TQFP, 44-VQFP
For Use With
ATSTK600-TQFP44 - STK600 SOCKET/ADAPTER 44-TQFPATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATMEGA16-16AUR
Manufacturer:
Encoders
Quantity:
101
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8-bit
Timer/Counter
Register
Description
Timer/Counter Control
Register – TCCR2
2466T–AVR–07/10
• Bit 7 – FOC2: Force Output Compare
The FOC2 bit is only active when the WGM bits specify a non-PWM mode. However, for ensur-
ing compatibility with future devices, this bit must be set to zero when TCCR2 is written when
operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate compare
match is forced on the waveform generation unit. The OC2 output is changed according to its
COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the
value present in the COM21:0 bits that determines the effect of the forced compare.
A FOC2 strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR2 as TOP.
The FOC2 bit is always read as zero.
• Bit 3, 6 – WGM21:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used. Modes of operation supported
by the Timer/Counter unit are: Normal mode, Clear Timer on Compare match (CTC) mode, and
two types of Pulse Width Modulation (PWM) modes. See
page
Table 50. Waveform Generation Mode Bit Description
Note:
• Bit 5:4 – COM21:0: Compare Match Output Mode
These bits control the Output Compare pin (OC2) behavior. If one or both of the COM21:0 bits
are set, the OC2 output overrides the normal port functionality of the I/O pin it is connected to.
However, note that the Data Direction Register (DDR) bit corresponding to OC2 pin must be set
in order to enable the output driver.
Bit
Read/Write
Initial Value
Mode
0
1
2
3
122.
1. The CTC2 and PWM2 bit definition names are now obsolete. Use the WGM21:0 definitions.
WGM21
(CTC2)
However, the functionality and location of these bits are compatible with previous versions of
the timer.
0
0
1
1
FOC2
W
7
0
WGM20
(PWM2)
WGM20
0
1
0
1
R/W
6
0
Timer/Counter Mode of
Operation
Normal
PWM, Phase Correct
CTC
Fast PWM
COM21
R/W
5
0
COM20
R/W
4
0
WGM21
R/W
3
0
(1)
0xFF
0xFF
OCR2
TOP
0xFF
CS22
R/W
2
0
Table 50
CS21
Update of
OCR2
Immediate
TOP
Immediate
BOTTOM
R/W
1
0
and
ATmega16(L)
“Modes of Operation” on
CS20
R/W
0
0
TOV2 Flag
Set on
MAX
BOTTOM
MAX
MAX
TCCR2
128
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