Z86D7308PSC1987 Zilog, Z86D7308PSC1987 Datasheet - Page 70

• Manufacturer Part Number: Z86D7308PSC1987
• Description: IC 32K OTP 3 VOLT 40-DIP
• Manufacturer: Zilog
• Series: Z8® IRr

Specifications of Z86D7308PSC1987

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, LVD, POR, WDT
• Number Of I /o: 31
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 236 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -

PS019401-1102
Watch-Dog Timer Mode Register (WDTMR)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its termi-
nal count. The WDT must initially be enabled by executing the WDT instruction.
On subsequent executions of the WDT instruction, the WDT is refreshed. The
WDT circuit is driven by an on-board RC oscillator or external oscillator from the
XTAL1 pin. The WDT instruction affects the Zero (Z), Sign (S), and Overflow (V)
flags.
The POR clock source is selected with bit 4 of the WDT register. Bits 0 and 1 con-
trol a tap circuit that determines the minimum timeout period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
STOP. Bits 5 through 7 are reserved (Figure 38). This register is accessible only
during the first 61 processor cycles (122 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode
Recovery (Figure 37). After this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register Group at address location
organized as shown in Figure 38.
Figure 38. Watch-Dog Timer Mode Register (Write Only)
D7
* Default setting after reset
WDTMR (0F) 0F
D6
D5
D4
P
D3
R
E
D2
L
D1
I
M
D0
I
N
A
40/44/48-Pin Low-Voltage IR OTP
WDT TAP INT RC OSC
00
01*
10
11
WDT During HALT
0 OFF
1 ON *
WDT During STOP
0 OFF
1 ON *
Reserved (Must be 0)
Reserved (Must be 0)
R
Y
80 ms min
20 ms min
10 ms min
5 ms min
0Fh
Z86D73
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