LH75410N0M100C0 Sharp Microelectronics, LH75410N0M100C0 Datasheet - Page 64
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LH75410N0M100C0
Manufacturer Part Number
LH75410N0M100C0
Description
IC ARM7 BLUESTREAK MCU 144TQFP
Manufacturer
Sharp Microelectronics
Series
BlueStreak ; LH7r
Specifications of LH75410N0M100C0
Core Processor
ARM7
Core Size
16/32-Bit
Speed
84MHz
Connectivity
EBI/EMI, SPI, SSI, SSP, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, LCD, POR, PWM, WDT
Number Of I /o
76
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.7 V ~ 3.6 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
144-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Other names
425-1862
LH75410N0M100
SM75410C0-M-100-30
LH75410N0M100
SM75410C0-M-100-30
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LH75410N0M100C0
Manufacturer:
Sharp Microelectronics
Quantity:
10 000
LH75400/01/10/11
MEMORY CONTROLLER WAVEFORMS
Static Memory Controller Waveforms
External Static Memory Write, with one Wait State. Fig-
ure 14 shows the waveform and timing for an External
Static Memory Write, with two Wait States. Figure 15
shows the waveform and timing for an External Static
Memory Read, with one Wait State.
by an external device to extend the wait time during a
memory access. The SMC samples nWAIT at the
beginning of at the beginning of each system clock
cycle. The system clock cycle in which the nCSx signal
is asserted counts as the first wait state. See Figure 16.
The SMC recognizes that nWAIT is active within 2
clock cycles after it has been asserted. To assure that
the current access (read or write) will be extended by
nWAIT, program at least two wait states for this bank of
64
Figure 13 shows the waveform and timing for an
The SMC supports an nWAIT input that can be used
XTAL32
XTAL14
LREG
nPOR
VDD
PLL
VDDmin
VDDCmin
tLREG
tOSC14
Figure 12. Power-up Stabilization
tOSC32
tPORH
Version 1.2
memory. If N wait states are programmed, the SMC
holds this state for N system clocks or until the SMC
detects that nWAIT is inactive, whichever occurs last.
As the number of wait states programmed increases,
the amount of delay before nWAIT must be asserted
also increases. If only 2 wait states are programmed,
nWAIT must be asserted in the clock cycle immediately
following the clock cycle during which the nCSx signal
is asserted. Once the SMC detects that the external
device has deactivated nWAIT, the SMC completes its
access in 3 system clock cycles.
ing nCSx and asserting nWAIT is:
measurements are made from the Address Valid point
and HCLK is an internal signal, shown for reference only.
The formula for the allowable delay between assert-
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
The signal tIDD is shown without a setup time, as
System-on-Chip
Data Sheet
LH754xx-100