LH7A400N0F000B5 Sharp Microelectronics, LH7A400N0F000B5 Datasheet - Page 7

• Manufacturer Part Number: LH7A400N0F000B5
• Description: IC ARM9 BLUESTREAK MCU 256CABGA
• Manufacturer: Sharp Microelectronics
• Series: BlueStreak ; LH7Ar

Specifications of LH7A400N0F000B5

• Core Processor: ARM9
• Core Size: 32-Bit
• Speed: 200MHz
• Connectivity: Audio CODEC, EBI/EMI, IrDA, MMC, SmartCard, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 60
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 256-CABGA
• Data Bus Width: 32 bit
• Data Ram Size: 80 KB
• Maximum Clock Frequency: 250 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

32-Bit System-on-Chip
Data Sheet
PBGA
PIN
M2
M4
A9
B9
D9
E9
K1
K2
K3
K5
N1
N2
N3
P1
P2
R1
K6
F9
L1
L2
L3
L4
L5
L7
L8
T1
J5
CABGA
C11
PIN
C9
M1
M2
M3
N1
N2
M4
R1
M5
N4
A9
B9
A8
K1
K2
K3
K4
K6
K5
P1
P2
P3
L1
L2
L3
L5
nRAS
DQM0
DQM1
DQM2
DQM3
PA0/LCDVD16
PA1/LCDVD17
PA2
PA3
PA4
PA5
PA6
PA7
PB0/UARTRX1
PB1/UARTTX3
PB2/UARTRX3
PB3/
UARTCTS3
PB4/
UARTDCD3
PB5/
UARTDSR3
PB6/SWID/
SMBD
PB7/SMBCLK
PC0/UARTTX1
PC1/LCDPS
PC2/
LCDVDDEN
PC3/LCDREV
PC4/LCDSPS
PC5/LCDCLS
SIGNAL
Synchronous Memory Row Address Strobe Signal HIGH
Synchronous Memory Data Mask 0
Synchronous Memory Data Mask 1
Synchronous Memory Data Mask 2
Synchronous Memory Data Mask 3
• GPIO Port A
• LCD Data bit 16. This CLCDC output signal is
• GPIO Port A
• LCD Data bit 17. This CLCDC output signal is
GPIO Port A
• GPIO Port B
• UART1 Receive Data Input
• GPIO Port B
• UART3 Transmit Data Out
• GPIO Port B
• UART3 Receive Data In
• GPIO Port B
• UART3 Clear to Send
• GPIO Port B
• UART3 Data Carrier Detect
• GPIO Port B
• UART3 Data Set Ready
• GPIO Port B
• Single Wire Data
• Smart Battery Data
• GPIO Port B
• Smart Battery Clock
• GPIO Port C
• UART1 Transmit Data Output
• GPIO Port C
• HR-TFT Power Save
• GPIO Port C
• HR-TFT Power Sequence Control
• GPIO Port C
• HR-TFT Gray Scale Voltage Reverse
• GPIO Port C
• HR-TFT Reset Row Driver Counter
• GPIO Port C
• HR-TFT Row Driver Clock
always LOW.
always LOW.
Table 1. Functional Pin List (Cont’d)
DESCRIPTION
Version 1.0
HIGH
HIGH
HIGH
HIGH
Input
Input: PA0
Input: PA1
Input: PB0
Input: PB1
Input: PB2
Input: PB3
Input: PB4
Input: PB5
Input: PB6
Input: PB7
LOW: PC0
LOW: PC1
LOW: PC2
LOW: PC3
LOW: PC4
LOW: PC5
RESET
STATE
HIGH
HIGH
HIGH
HIGH
HIGH
No Change
No Change
No Change
No Change
LOW if
UART3 is
Enabled,
otherwise
No Change
No Change
No Change
No Change
No Change
Input if SMB
is Enabled,
otherwise
No Change
Input if SMB
is Enabled,
otherwise
No Change
No Change
No Change
No Change
No Change
No Change
No Change
STANDBY
STATE
LH7A400
OUTPUT
DRIVE
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
12 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
8 mA
7