ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet - Page 47

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ZLP32300H4832G

Manufacturer Part Number
ZLP32300H4832G
Description
IC CRIMZON Z8 MCU OTP 32K 48SSOP
Manufacturer
Zilog
Series
Crimzon™ ZLPr
Datasheets

Specifications of ZLP32300H4832G

Core Processor
Z8
Core Size
8-Bit
Speed
8MHz
Peripherals
Brown-out Detect/Reset, HLVD, POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Ram Size
237 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
48-SSOP
Data Bus Width
8 bit
Data Ram Size
237 B
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
32
Number Of Timers
2
Operating Supply Voltage
2 V to 3.6 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
0 C
For Use With
269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details
Other names
269-4510
ZLP32300H4832G
PS020823-0208
T16_OUT
CTR1, D2
Interrupts
CTR1 D3
Initiating PING-PONG Mode
First, make sure both counter/timers are not running. Set T8 into SINGLE-PASS mode
(CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the PING-PONG
mode (CTR1, D2; D3). These instructions can be in random order. Finally, start PING-
PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2, D7), see
The initial value of T8 or T16 must not be
reload the initial value to avoid an unknown previous value.
During PING-PONG Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alternately by
hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the counter/timers
reach the terminal count.
Timer Output
The output logic for the timers is displayed in
when D0 of CTR0 is set. P35 is used to output the value of TI6-OUT when D0 of CTR2 is
set. When D6 of CTR1 is set, P36 outputs the logic combination of T8-OUT and T16-
OUT determined by D5 and D4 of CTR1.
The Crimzon ZLP32300 features six different interrupts (see
interrupts are maskable and prioritized (see
lows: three sources are claimed by Port 3 lines P33–P31, two by the
T8_OUT
MUX
AND/OR/NOR/NAND
Figure 27. Output Circuit
CTR1 D5, D4
Logic
1
Figure
. If you stop the timer and restart the timer,
P34_Internal
P36_Internal
P35_Internal
Figure
28). The six sources are divided as fol-
27. P34 is used to output T8-OUT
Table 11
Product Specification
Crimzon
CTR0 D0
CTR1 D6
CTR2 D0
Functional Description
on page 45). The
MUX
MUX
MUX
Figure
®
ZLP32300
26.
P34
P36
P35
43

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