ZLP32300H4832G Zilog, ZLP32300H4832G Datasheet - Page 53

• Manufacturer Part Number: ZLP32300H4832G
• Description: IC CRIMZON Z8 MCU OTP 32K 48SSOP
• Manufacturer: Zilog
• Series: Crimzon™ ZLPr

Specifications of ZLP32300H4832G

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 8MHz
• Peripherals: Brown-out Detect/Reset, HLVD, POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Ram Size: 237 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 48-SSOP
• Data Bus Width: 8 bit
• Data Ram Size: 237 B
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• For Use With: 269-4665 - KIT REMOTE UNVRSL USA 6-FUNCTION
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4510; ZLP32300H4832G

PS020823-0208
Stop Mode Recovery
Stop Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop Mode Recov-
ery (see
bit that is hardware set on the condition of Stop recovery and reset by a power-on cycle.
Bit 6 controls whether a low level or a high level at the XOR-gate input (see
page 52) is required from the recovery source. Bit 5 controls the reset delay after recovery.
Bits D2, D3, and D4 of the SMR register specify the source of the Stop Mode Recovery
signal. Bits D0 determines if SCLK/TCLK are divided by 16 or not. The SMR is located
in Bank F of the Expanded Register Group at address
SMR(0F)0Bh
D7
*Default after Power-On Reset or Watchdog Reset
* *Default setting after Reset and Stop Mode Recovery.
* * *At the XOR gate input
* * * *Default setting after reset. Must be 1 if using a crystal or resonator clock source.
D6
Figure
D5
Figure 31. Stop Mode Recovery Register
31). All bits are write only except bit 7, which is read only. Bit 7 is a Flag
D4
D3
D2
D1
D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
0Bh
.
Product Specification
Crimzon
Functional Description
®
Figure 33
ZLP32300
on
49