STR755FV2H6 STMicroelectronics, STR755FV2H6 Datasheet - Page 65
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STR755FV2H6
Manufacturer Part Number
STR755FV2H6
Description
MCU 32BIT 256K FLASH 100-LFBGA
Manufacturer
STMicroelectronics
Series
STR7r
Datasheet
1.STR750FV0T6.pdf
(84 pages)
Specifications of STR755FV2H6
Core Processor
ARM7
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, SPI, SSI, SSP, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
72
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LFBGA
For Use With
MCBSTR750UME - BOARD EVAL MCBSTR750 + ULINK-MEMCBSTR750U - BOARD EVAL MCBSTR750 + ULINK2497-5748 - BOARD EVALUATION FOR STR750XF
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
497-5871
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STR755FV2H6
Manufacturer:
STMicroelectronics
Quantity:
10 000
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
SSP synchronous serial peripheral in slave mode (SPI or TI mode)
Subject to general operating conditions with C
Table 39.
1. Data based on characterisation results, not tested in production.
Figure 33. SPI configuration, slave mode with CPHA=0, single transfer
MISO
MOSI
t
Symbol
t
t
t
t
t
t
su(MOSI)
NSSLQV
t
NSSLQZ
su(NSS)
h(MOSI)
SCKQV
SCKQX
h(NSS)
f
SCK
NSS
CPHA=0
CPOL=0
CPHA=0
CPOL=1
OUTPUT
INPUT
INPUT
DONT CARE
SPI clock frequency
NSS input setup time w.r.t
SCK first edge
NSS input hold time w.r.t
SCK last edge
NSS low to Data Output
MISO valid time
NSS low to Data Output
MISO invalid time
SCK trigger edge to data
output MISO valid time
SCK trigger edge to data
output MISO invalid time
MOSI setup time w.r.t SCK
sampling edge
MOSI hold time w.r.t SCK
sampling edge
SSP slave mode characteristics
t
z
NSSLQV
t
su(NSS)
Parameter
t
su(SI)
sample
edge
MSB IN
t
h(SI)
t
t
w(SCKH)
w(SCKL)
MSB OUT
trigger
t
SCKQV(MISO)
edge
t
c(SCK)
Conditions
BIT OUT
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
SSP0
SSP1
L
(1)
≈
45 pF
BIT1 IN
3t
3t
t
t
PCLK
PCLK
PCLK
PCLK
t
SCKQX(MISO)
2t
2t
2t
2t
2t
2t
Min
PCLK
PCLK
PCLK
PCLK
PCLK
PCLK
0
0
0
0
+15ns
+15ns
+15 ns
+15 ns
sample
edge
t
t
r(SCK)
f(SCK)
Electrical parameters
LSB IN
3t
3t
3t
3t
(f
LSB OUT
2.66 MHz
PCLK
PCLK
PCLK
PCLK
trigger
PLCK
edge
Max
t
15
30
h(NSS)
+30 ns
+30 ns
+15 ns
+15 ns
/12)
t
NSSHQZ
DONT CARE
MHz
Unit
ns
65/84
z