UPSD3234A-40U6T STMicroelectronics, UPSD3234A-40U6T Datasheet - Page 72
UPSD3234A-40U6T
Manufacturer Part Number
UPSD3234A-40U6T
Description
IC MCU 8032 64KB FLASH 80TQFP
Manufacturer
STMicroelectronics
Series
µPSDr
Datasheet
1.UPSD3234A-40U6T.pdf
(189 pages)
Specifications of UPSD3234A-40U6T
Core Processor
8032
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, UART/USART, USB
Peripherals
LVR, POR, PWM, WDT
Number Of I /o
46
Program Memory Size
288KB (288K x 8)
Program Memory Type
FLASH
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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Standard serial interface (UART)
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as data bits shift out to the right, zeros are clocked in from the left. When TB8 is at the out-
put position of the shift register, then the Stop bit is just to the left of TB8, and all positions to
the left of that contain zeros. This condition flags the TX Control unit to do one last shift and
then deactivate SEND and set TI. This occurs at the 11th divide-by 16 rollover after “WRITE
to SUBF.”
Reception is initiated by a detected 1-to-0 transition at RxD. For this purpose RxD is
sampled at a rate of 16 times whatever baud rate has been established. When a transition is
detected, the divide-by-16 counter is immediately reset, and 1FFH is written to the input shift
register.
At the 7th, 8th, and 9th counter states of each bit time, the bit detector samples the value of
R-D. The value accepted is the value that was seen in at least 2 of the 3 samples. If the
value accepted during the first bit time is not '0,' the receive circuits are reset and the unit
goes back to looking for another 1-to-0 transition. If the Start bit proves valid, it is shifted into
the input shift register, and reception of the rest of the frame will proceed.
As data bits come in from the right, '1s' shift out to the left. When the Start bit arrives at the
left-most position in the shift register (which in Modes 2 and 3 is a 9-bit register), it flags the
RX Control block to do one last shift, load SBUF and RB8, and set RI.
The signal to load SBUF and RB8, and to set RI, will be generated if, and only if, the
following conditions are met at the time the final shift pulse is generated:
1.
2.
If either of these conditions is not met, the received frame is irretrievably lost, and RI is not
set. If both conditions are met, the received 9th data bit goes into RB8, and the first 8 data
bits go into SBUF. One bit time later, whether the above conditions were met or not, the unit
goes back to looking for a 1-to-0 transition at the RxD input.
RI = 0, and
Either SM2 = 0, or the received 9th data bit = 1
UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV
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