UPSD3234A STMicroelectronics, UPSD3234A Datasheet

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UPSD3234A

Manufacturer Part Number
UPSD3234A
Description
Manufacturer
STMicroelectronics
Datasheet

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FEATURES SUMMARY
September 2003
Rev. 1.2
The uPSD323X Devices combine a Flash PSD
architecture with an 8032 microcontroller core.
The uPSD323X Devices of Flash PSDs feature
dual banks of Flash memory, SRAM, general
purpose I/O and programmable logic, supervi-
sory functions and access via USB, I
DDC and PWM channels, and an on-board
8032 microcontroller core, with two UARTs,
three 16-bit Timer/Counters and two External
Interrupts. As with other Flash PSD families, the
uPSD323X Devices are also in-system pro-
grammable (ISP) via a JTAG ISP interface.
Large 8KByte SRAM with battery back-up
option
Dual bank Flash memories
– 128KByte or 256KByte main Flash memory
– 32KByte secondary Flash memory
Content Security
– Block access to Flash memory
Programmable Decode PLD for flexible address
mapping of all memories within 8032 space.
High-speed clock standard 8032 core (12-cycle)
USB Interface (some devices only)
I
5 Pulse Width Modulator (PWM) channels
Analog-to-Digital Converter (ADC)
Standalone Display Data Channel (DDC)
Six I/O ports with up to 46 I/O pins
3000 gate PLD with 16 macrocells
Supervisor functions with Watchdog Timer
In-System Programming (ISP) via JTAG
Zero-Power Technology
Single Supply Voltage
– 4.5 to 5.5V
– 3.0 to 3.6V
2
C interface for peripheral connections
2
C, ADC,
Flash Programmable System Devices
UPSD3234A, UPSD3234BV
UPSD3233B, UPSD3233BV
with 8032 Microcontroller Core
Figure 1. 52-lead, Thin, Quad, Flat Package
Figure 2. 80-lead, Thin, Quad, Flat Package
TQFP80 (U)
TQFP52 (T)
1/175

Related parts for UPSD3234A

UPSD3234A Summary of contents

Page 1

... In-System Programming (ISP) via JTAG Zero-Power Technology Single Supply Voltage – 4.5 to 5.5V – 3.0 to 3.6V September 2003 Rev. 1.2 UPSD3234A, UPSD3234BV UPSD3233B, UPSD3233BV Flash Programmable System Devices with 8032 Microcontroller Core Figure 1. 52-lead, Thin, Quad, Flat Package 2 C, ADC, Figure 2. 80-lead, Thin, Quad, Flat Package ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV TABLE OF CONTENTS SUMMARY DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 uPSD323X Devices Product Matrix (Table 1 TQFP52 Connections (Figure 3 TQFP80 Connections (Figure 4 80-Pin Package Pin Description (Table 2 PIN PACKAGE I/O PORT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 ARCHITECTURE OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Memory Map and Address Space (Figure 5 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8032 MCU Registers (Figure 6 Configuration of BA 16-bit Registers (Figure 7 ...

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... Interrupt Priority Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Interrupts Enable Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Priority Levels (Table 19 Description of the IE Bits (Table 20.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Description of the IEA Bits (Table 21 Description of the IP Bits (Table 22.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Description of the IPA Bits (Table 23 How Interrupts are Handled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Vector Addresses (Table 24 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 3/175 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV POWER-SAVING MODE Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power-Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Power-Saving Mode Power Consumption (Table 25 Power Control Register Pin Status During Idle and Power-down Mode (Table 26 Description of the PCON Bits (Table 27 Idle Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 I/O PORTS (MCU Module I/O Port Functions (Table 28 P1SFS (91H) (Table 29 ...

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... A/D Block Diagram (Figure 35.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 ADC SFR Memory Map (Table 46 Description of the ACON Bits (Table 47 ADC Clock Input (Table 48 PULSE WIDTH MODULATION (PWM 4-channel PWM Unit (PWM 0- Four-Channel 8-bit PWM Block Diagram (Figure 36 PWM SFR Memory Map (Table 49 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 5/175 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Programmable Period 8-bit PWM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Programmable PWM 4 Channel Block Diagram (Figure 37 PWM 4 Channel Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 PWM 4 With Programmable Pulse Width and Frequency (Figure 38 I2C INTERFACE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Block Diagram of the I2C Bus Serial I/O (Figure 39 Serial Control Register (SxCON: S1CON, S2CON) (Table 50 Description of the SxCON Bits (Table 51 ...

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... Register Address Offset (Table 84 105 PSD MODULE DETAILED OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 MEMORY BLOCKS 106 Primary Flash Memory and Secondary Flash memory Description . . . . . . . . . . . . . . . . . . . . 106 Memory Block Select Signals 106 Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Instructions (Table 85 108 Power-down Instruction and Power-up Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 7/175 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV READ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Status Bit (Table 86 110 Programming Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Data Polling Flowchart (Figure 52 111 Data Toggle Flowchart (Figure 53 112 Erasing Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Specific Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 Sector Protection/Security Bit Definition – Flash Protection Register (Table 87 114 Sector Protection/Security Bit Definition – ...

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... Warm RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 I/O Pin, Register and PLD Status at RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139 Reset of Flash Memory Erase and Program Cycles 139 Reset (RESET) Timing (Figure 71 139 Status During Power-on RESET, Warm RESET and Power-down Mode (Table 105.). . . . . . . . . 140 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 9/175 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PROGRAMMING IN-CIRCUIT USING THE JTAG SERIAL INTERFACE . . . . . . . . . . . . . . . . . . . . . 141 Standard JTAG Signals 141 JTAG Port Signals (Table 106.). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 JTAG Extensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Security and Flash memory Protection 141 INITIAL DELIVERY STATE 141 AC/DC PARAMETERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 PLD ICC /Frequency Consumption (5V range) (Figure 72 142 PLD ICC /Frequency Consumption (3V range) (Figure 73 ...

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... Recommended Oscillator Circuits (Figure 90 168 PSD MODULE AC Measurement I/O Waveform (Figure 91 168 PSD MODULEAC Measurement Load Circuit (Figure 92 168 Capacitance (Table 141 168 PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 PACKAGE MECHANICAL INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170 REVISION HISTORY 174 Device Functional Change History (Table 146 174 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 11/175 ...

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... High-speed clock standard 8032 core (12-cycle) – 40MHz operation at 5V, 24MHz at 3.3V – 2 UARTs with independent baud rate, three 16-bit Timer/Counters and two External Inter- rupts USB Interface (uPSD3234A-40 only) – Supports USB 1.1 Slow Mode (1.5Mbit/s) – Control endpoint 0 and interrupt endpoints 1 and 2 2 ...

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... PC7 2 PC6 3 PC5 4 (1) USB– 5 PC4 6 (2) USB GND 9 PC3 10 PC2 11 PC1 12 PC0 13 Note: 1. Pull-up resistor required on pin 5 (2k 2. Pin 7 is Not Connected (NC) for device with no USB function. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Macro I/O PWM Timer UART -Cells Pins Ch. / Ctr Ch ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 4. TQFP80 Connections PD2 1 P3.3 /EXINT1 2 PD1 3 PD0, ALE 4 PC7 5 PC6 6 PC5 7 (1) USB- 8 PC4 9 (2) USB GND 13 PC3 14 PC2 15 PC1 P4.7 / PWM4 18 P4.6 / PWM3 19 PC0 20 Note Not Connected 1. Pull-up resistor required on pin 8 (2k 2. Pin 10 is Not Connected (NC) for device with no USB function. ...

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... P3.7 SCL2 46 P4.0 SDA1 33 P4.1 SCL1 31 P4.2 VSYNC 30 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV In/Out Basic External Bus I/O Multiplexed Address/Data bus A1/D1 I/O Multiplexed Address/Data bus A0/D0 I/O Multiplexed Address/Data bus A2/D2 I/O Multiplexed Address/Data bus A3/D3 I/O Multiplexed Address/Data bus A4/D4 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Signal Port Pin Pin No. Name P4.3 PWM0 27 P4.4 PWM1 25 P4.5 PWM2 23 P4.6 PWM3 19 P4.7 PWM4 18 USB- 8 USB+ 10 AVREF 70 RD_ 65 WR_ 62 PSEN_ 63 ALE 4 RESET_ 68 XTAL1 48 XTAL2 49 PA0 35 PA1 34 PA2 32 PA3 28 PA4 26 PA5 24 PA6 22 PA7 21 16/175 In/Out Basic I/O ...

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... The 52-pin package members of the uPSD323X Devices have the same port pins as those of the 80-pin package except: Port 0 (P0.0-P0.7, external address/data bus AD0-AD7) Port 2 (P2.0-P2.3, external address bus A8- A11) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV In/Out Basic I/O General I/O port pin I/O General I/O port pin ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ARCHITECTURE OVERVIEW Memory Organization The uPSD323X Devices’s standard 8032 Core has separate 64KB address spaces for Program memory and Data Memory. Program memory is where the 8032 executes instructions from. Data memory is used to hold data variables. Flash memory can be mapped in either program or data space ...

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... Bit 8 Bit 7 00h SP Hardware Fixed SP (Stack Pointer) could be in 00h-FFh UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Program Counter. The Program Counter is a 16- bit wide which consists of two 8-bit registers, PCH and PCL. This counter indicates the address of the next instruction to be executed. In RESET state, the program counter has reset routine address (PCH:00h, PCL:00h) ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 9. PSW (Program Status Word) Register Carry Flag Auxillary Carry Flag General Purpose Flag Program Memory The program memory consists of two Flash mem- ory: 128 KByte (or 256 KByte) Main Flash and 32 KByte of Secondary Flash. The Flash memory can be mapped to any address space as defined by the user in the PSDsoft Tool ...

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... Register Bank 2 10h 0Fh Register Bank 1 08h 07h Register Bank 0 00h UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Addressing Modes The addressing modes in uPSD323X Devices in- struction set are as follows Direct addressing Indirect addressing Register addressing Register-specific addressing Immediate constants addressing Indexed addressing ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV (3) Register addressing. The containing registers R0 through R7, can be ac- cessed by certain instructions which carry a 3-bit register specification within the opcode of the in- struction. Instructions that access the registers this way are code efficient, since this mode elimi- nates an address byte. When the instruction is ex- ecuted, one of four banks is selected at execution time by the two bank select bits in the PSW ...

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... Data Memory space with- out going through the Accumulator. The XRL <byte>, #data instruction, for example, offers a quick and easy way to invert port bits XRL P1, #0FFH. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Operation Dir <byte> <byte> – <byte> – < ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 5. Logical Instructions Mnemonic ANL A,<byte> ANL <byte>,A ANL <byte>,#data ORL A,<byte> ORL <byte>,A ORL <byte>,#data XRL A,<byte> XRL <byte>,A XRL <byte>,#data CRL A CPL RLC A Rotate A Left through Carry RR A RRC A Rotate A Right through Carry ...

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... XCH A,<byte> Exchange contents of A and <byte> XCHD A,@Ri Exchange low nibbles of A and @Ri UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The XCH A, <byte> instruction causes the Accu- mulator and ad-dressed byte to exchange data. The XCHD A, @Ri instruction is similar, but only the low nibbles are involved in the exchange. To ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV First, pointers R1 and R0 are set up to point to the two bytes containing the last four BCD digits. Then a loop is executed which leaves the last byte, loca- tion 2EH, holding the last two digits of the shifted number. The pointers are decremented, and the loop is repeated for location 2DH ...

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... MOVX @DPTR,a Table 11. Lookup Table READ Instruction Mnemonic MOVC A,@A+DPTR MOVC A,@A+PC UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV copies the desired table entry into the Accumula- tor. The other MOVC instruction works the same way, except the Program Counter (PC) is used as the table base, and the table is accessed through a ...

Page 28

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Boolean Instructions The uPSD323X Devices contain a complete Bool- ean (single-bit) processor. One page of the inter- nal RAM contains 128 address-able bits, and the SFR space can support up to 128 addressable bits as well. All of the port lines are bit-addressable, and each one can be treated as a separate single- bit port ...

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... MOV DPTR,#JUMP TABLE MOV A,INDEX_NUMBER RL A JMP @A+DPTR UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The RL A instruction converts the index number (0 through even number on the range 0 through 8, because each entry in the jump table is 2 bytes long: JUMP TABLE: ...

Page 30

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 14 shows the list of conditional jumps avail- able to the uPSD323X Devices user. All of these jumps specify the destination address by the rela- tive offset method, and so are limited to a jump dis- tance of -128 to +127 bytes from the instruction following the conditional jump instruction ...

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... Read opcode 1-Byte, 1-Cycle Instruction, e.g. INC A Read opcode 2-Byte, 1-Cycle Instruction, e.g. ADD A, adrs Read opcode 1-Byte, 2-Cycle Instruction, e.g. INC DPTR Read opcode (MOVX 1-Byte, 2-Cycle MOVX Instruction UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Read next Read next opcode and ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV UPSD3200 HARDWARE DESCRIPTION The uPSD323X Devices has a modular architec- ture with two main functional modules: the MCU Module and the PSD Module. The MCU Module consists of a standard 8032 core, peripherals and other system supporting functions. The PSD Mod- ule provides configurable Program and Data mem- ories to the 8032 CPU core ...

Page 33

... TMOD TCON ( Note: 1. Register can be bit addressing UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV – ADC – I/O Ports – USB Special Function Registers A map of the on-chip memory area called the Spe- cial Function Register (SFR) space is shown in Ta- ble 15. Note: In the SFRs not all of the addresses are oc- cupied ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 16. List of all SFR SFR Reg Name Addr DPL 83 DPH 87 PCON SMOD SMOD1 LVREN ADSFINT RCLK1 88 TCON TF1 TR1 89 TMOD Gate C/T 8A TL0 8B TL1 8C TH0 8D TH1 P1SFS P1S7 P1S6 93 P3SFS P3S7 P3S6 94 P4SFS P4S7 P4S6 95 ASCL 96 ADAT ...

Page 35

... AA PWM4P AB PWM4W AE WDKEY PSCL0L B2 PSCL0H B3 PSCL1L B4 PSCL1H B7 IPA PDDC T2CON TF2 EXF2 C9 T2MOD UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name ES2 ET2 ES ET1 EX1 PS2 PT2 PS PT1 PX1 RCLK TCLK EXEN2 TR2 Reset Comments Value 1 0 PWM0 00 Output Duty Cycle PWM1 ...

Page 36

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV SFR Reg Name Addr RCAP2L CB RCAP2H CC TL2 CD TH2 D0 PSW S1SETUP D2 S2SETUP D4 RAMBUF D5 DDCDAT D6 DDCADR D7 DDCCON — EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT D8 S1CON CR2 ENI1 D9 S1STA GC Stop DA S1DAT DB S1ADR DC S2CON CR2 EN1 DD S2STA GC Stop DE S2DAT DF S2ADR E0 ACC ...

Page 37

... ED USTA RSEQ SETUP EE UADR USBEN UADD6 UADD5 UADD4 EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UDR0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name RSTF TXD0F RXD0F RXD1F RSTFIE TXD0IE RXD0IE TXD1IE TX0E RX0E TP0SIZ3 TP0SiZ2 TP0SIZ1 TP0SIZ0 — FRESUM TP1SIZ3 TP1SiZ2 TP1SIZ1 TP1SIZ0 — ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 17. PSD Module Register Address Offset CSIOP Addr Register Name 7 Offset 00 Data In (Port A) 02 Control (Port A) Configure pin between I/O or Address Out Mode. Bit = 0 selects I/O 04 Data Out (Port A) 06 Direction (Port A) Configures Port pin as input or output. Bit = 0 selects input Configures Port pin between CMOS, Open Drain or Slew rate ...

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... PMMR0 * B4 PMMR2 * E0 Page Periph mode Note: (Register address = csiop address + address offset; where csiop address is defined by user in PSDsoft) * indicates bit is not used and need to set to '0.' UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name Sec6_ Sec5_ Sec4_ Sec3_ Sec2_ Prot Prot Prot ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV INTERRUPT SYSTEM There are interrupt requests from 10 sources as follows. INT0 external interrupt 2nd USART Interrupt Timer 0 Interrupt Interrupt INT1 External Interrupt (or ADC Interrupt) DDC Interrupt Timer 1 Interrupt USB Interrupt USART Interrupt Timer 2 Interrupt External Int0 The INT0 can be either level-active or transition- active depending on Bit IT0 in register TCON ...

Page 41

... DDC Timer 1 USB 2nd USART Timer 2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV determine the source and clear the corresponding flag. Both USART’s are identical, except for the additional interrupt controls in the Bit 4 of the additional interrupt control registers (A7H, B7H IPA Priority ...

Page 42

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 18. SFR Register SFR Reg Addr Name IEA EDDC — — B7 IPA PDDC — — — Interrupt Priority Structure Each interrupt source can be assigned one of two priority levels. Interrupt priority levels are defined by the interrupt priority special function register IP and IPA ...

Page 43

... PDDC DDC Interrupt priority level 6 — Not used 5 — Not used 4 PS2 2nd USART Interrupt priority level 3 — Not used 2 — Not used 1 PI2C I²C Interrupt priority level 0 PUSB USB Interrupt priority level UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Function Function Function 43/175 ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV How Interrupts are Handled The interrupt flags are sampled at S5P2 of every machine cycle. The samples are polled during fol- lowing machine cycle. If one of the flags was in a set condition at S5P2 of the preceding cycle, the polling cycle will find it and the interrupt system will ...

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... TCLK1 1 PD Activate Power-down Mode (High enable) 0 IDL Activate Idle Mode (High enable) Note: 1. See the T2CON register for details of the flag description UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV – USART – 8-bit ADC 2 – Interface Note: Interrupt or RESET terminates the Idle Mode. ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Idle Mode The instruction that sets PCON.0 is the last in- struction executed in the normal operating mode before Idle Mode is activated. Once in the Idle Mode, the CPU status is preserved in its entirety: Stack pointer, Program counter, Program status word, Accumulator, RAM and All other registers maintain their data during Idle Mode ...

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... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV functions are controlled using the P1SFS register, except for Timer 2 and the 2nd UART which are enabled by their configuration registers. P1.0 to P1.3 are default to GPIO after reset. Port 3 pins 6 and 7 have been modified from the standard 8032 ...

Page 48

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PORT Type and Description Figure 17. PORT Type and Description (Part Symbol Out RESET I WR, RD,ALE, O PSEN XTAL1, I XTAL2 O PORT0 I/O 48/175 Circuit • Schmitt input with internal pull-up CMOS compatible interface NFC : 400ns NFC Output only On-chip oscillator ...

Page 49

... PORT1 <3:0>, I/O PORT3, PORT4<7:3,1:0> PORT2 PORT1 < 7:4 > I/O PORT4.2 I/O USB - , I/O USB + UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Circuit an_enb + – Function Bidirectional I/O port with internal pull-ups Schmitt input CMOS compatible interface Bidirectional I/O port with internal pull-ups Schmitt input ...

Page 50

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV OSCILLATOR The oscillator circuit of the uPSD323X Devices is a single stage inverting amplifier in a Pierce oscil- lator configuration. The circuitry between XTAL1 and XTAL2 is basically an inverter biased to the transfer point. Either a crystal or ceramic resonator can be used as the feedback element to complete Figure 19 ...

Page 51

... On initial power-up the LVR is enabled (default). After power-up the LVR can be disabled via the LVREN Bit in the PCON Reg- ister. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Note: The LVR logic is still functional in both the Idle and Power-down Modes. The reset threshold: 5V operation: 3 ...

Page 52

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV WATCHDOG TIMER The hardware watchdog timer (WDT) resets the uPSD323X Devices when it overflows. The WDT is intended as a recovery method in situations where the CPU may be subjected to a software upset. To prevent a system reset the timer must be reloaded in time by the application software. If the processor suffers a hardware/software malfunc- tion, the software will fail to reload the timer ...

Page 53

... WDRST6 This value is loaded to the 7 most significant bits of the 22-bit counter. WDRST0 For example: MOV WDRST,#1EH Note: The Watchdog Timer (WDT) is enabled at power-up or reset and must be served or disabled. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The RESET pulse width OSC Reset pulse width (about 10ms at 40Mhz, about 50ms at 8Mhz) Reset period (1 ...

Page 54

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV TIMER/COUNTERS (TIMER 0, TIMER 1 AND TIMER 2) The uPSD323X Devices has three 16-bit Timer/ Counter registers: Timer 0, Timer 1 and Timer 2. All of them can be configured to operate either as timers or event counters and are compatible with standard 8032 architecture. In the “Timer” function, the register is incremented every machine cycle ...

Page 55

... M0 (M1,M0)=(1,1): TL0 is an 8-bit Timer/Counter controlled by the standard TImer 0 control bits. TH0 is an 8-bit timer only controlled by Timer 1 control bits UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ter TCON (TCON Control Register). GATE is in TMOD. The 13-bit register consists of all 8 bits of TH1 and the lower 5 bits of TL1 ...

Page 56

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 22. Timer/Counter Mode 0: 13-bit Counter f ÷ 12 OSC T1 pin TR1 Gate INT1 pin Figure 23. Timer/Counter Mode 2: 8-bit Auto-reload f ÷ 12 OSC T1 pin TR1 Gate INT1 pin 56/175 C TL1 (5 bits) C Control C TL1 (8 bits) C Control TH1 (8 bits) TH1 TF1 Interrupt (8 bits) ...

Page 57

... Timer 2 Like Timers 0 and 1, Timer 2 can operate as either an event timer event counter. This is se- lected by Bit C/T2 in the special function register T2CON. It has three operating modes: capture, UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV C TL0 (8 bits) C Control TH1 ...

Page 58

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 40. Timer/Counter 2 Control Register (T2CON TF2 EXF2 Table 41. Description of the T2CON Bits Bit Symbol Timer 2 overflow flag. Set by a Timer 2 overflow, and must be cleared by software. TF2 7 TF2 will not be set when either (RCLK, RCLK1)=1 or (TCLK, TCLK)=1 Timer 2 external flag set when either a capture or reload is caused by a negative transition on T2EX and EXEN2=1 ...

Page 59

... Auto- reload 16-bit Capture Baud Rate Generator 1 x Off x x Note: = falling edge Figure 25. Timer 2 in Capture Mode f ÷ 12 OSC C/ C/ pin TR2 Transition Detector T2EX pin EXEN2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV T2MOD T2CON P1.1 DECN EXEN T2EX ...

Page 60

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 26. Timer 2 in Auto-Reload Mode f ÷ 12 OSC C/ C/ pin TR2 Transition Detector T2EX pin EXEN2 60/175 TH2 TL2 (8 bits) (8 bits) Control Reload RCAP2L RCAP2H Control TF2 Timer 2 Interrupt EXP2 AI06626 ...

Page 61

... Table 43. Serial Port Control Register (SCON SM0 SM1 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2 in all respects except baud rate. The baud rate in Mode 3 is variable. In all four modes, transmission is initiated by any instruction that uses SBUF as a destination regis- ter. Reception is initiated in Mode 0 by the condi- tion and REN = 1 ...

Page 62

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 44. Description of the SCON Bits Bit Symbol 7 SM0 (SM1,SM0)=(0,0): Shift Register. Baud rate = f (SM1,SM0)=(1,0): 8-bit UART. Baud rate = variable (SM1,SM0)=(0,1): 8-bit UART. Baud rate = f 6 SM1 (SM1,SM0)=(1,1): 8-bit UART. Baud rate = variable Enables the multiprocessor communication features in Mode 2 and 3. In Mode SM2 is set to '1,' RI will not be activated if its received 8th data bit (RB8 ...

Page 63

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV One can achieve very low baud rates with Timer 1 by leaving the Timer 1 Interrupt enabled, and con- figuring the Timer to run as a 16-bit timer (high nib- ble of TMOD = 0001B), and using the Timer 1 Interrupt 16-bit software reload ...

Page 64

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The timer can be configured for either “timer” or “counter” operation. In the most typical applica- tions configured for “timer” operation (C/T2 = 0). “Timer” operation is a little different for Timer 2 when it’s being used as a baud rate generator. ...

Page 65

... On receive, the data bit goes into RB8 in SCON. The baud rate is programma- UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ble to either 1/16 or 1/32 the CPU clock frequency in Mode 2. Mode 3 may have a variable baud rate generated from Timer 1 ...

Page 66

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ditions are met at the time the final shift pulse is generated and 2. Either SM2 = 0, or the received 9th data bit = 1 If either of these conditions is not met, the received frame is irretrievably lost, and RI is not set. If both Figure 27. Serial Port Mode 0, Block Diagram ...

Page 67

... Clear RI RI Receive Shift RxD (Data In) TxD (Shift Clock) Figure 29. Serial Port Mode 1, Block Diagram Timer1 Timer2 Overflow Overflow Write to SBUF ÷ SMOD 0 1 TCLK 0 1 RCLK RxD UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV S3P1 S6P1 TB8 Zero Detector Start ÷16 Tx Clock Serial Port Interrupt ÷ ...

Page 68

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 30. Serial Port Mode 1, Waveforms Tx Clock Write to SBUF S1P1 Send Data Shift Start Bit TxD T1 Rx Clock Start Bit RxD Bit Detector Sample Times Shift RI Figure 31. Serial Port Mode 2, Block Diagram Phase2 Clock 1/2*f OSC Write to SBUF ÷ ...

Page 69

... Start Bit RxD Bit Detector Sample Times Shift RI Figure 33. Serial Port Mode 3, Block Diagram Timer1 Timer2 Overflow Overflow Write to SBUF ÷ SMOD 0 1 TCLK 0 1 RCLK RxD UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ÷16 Reset TB8 Start ÷16 Tx Clock Serial Port Interrupt ÷16 Sample ...

Page 70

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 34. Serial Port Mode 3, Waveforms Tx Clock Write to SBUF S1P1 Send Data Shift Start Bit TxD TI Stop Bit Generator Rx Clock Start Bit RxD Bit Detector Sample Times Shift RI 70/175 ÷16 Reset TB8 Stop Bit RB8 Stop Bit Transmit ...

Page 71

... MUX ACH1 ACH2 ACH3 ACON UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The block diagram of the A/D module is shown in Figure 35. The A/D Status Bit ADSF is set auto- matically when A/D conversion is completed, cleared when A/D conversion is in process. The ASCL should be loaded with a value that re- ...

Page 72

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 46. ADC SFR Memory Map SFR Reg Addr Name 7 95 ASCL 96 ADAT ADAT7 ADAT6 97 ACON Table 47. Description of the ACON Bits Bit Symbol — Reserved ADEN ADC Enable Bit ADC shut off and consumes no operating current 5 4 — ...

Page 73

... PWML = 0). When the contents of this regis- ter is less than or equal to the counter value, the corresponding PWM output is set LOW (with PWML = 0). The pulse-width-ratio is therefore de- UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV fined by the contents of the corresponding Special Function Register (PWM 0- PWM. By load- ing the corresponding Special Function Register ...

Page 74

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 36. Four-Channel 8-bit PWM Block Diagram 8 16-bit Prescaler CPU rd/wr 16-bit Prescaler f /2 OSC load PWMCON bit5 (PWME) 74/175 DATA BUS 8-bit PWM0-PWM3 CPU rd/wr Data Registers 8-bit PWM0-PWM3 Comparators Registers 8-bit PWM0-PWM3 Register Comparators (B2h,B1h) 8 8-bit Counter ...

Page 75

... PWMCON Register Bit Definition: – PWML = PWM 0-3 polarity control – PWMP = PWM 4 polarity control – PWME = PWM enable (0 = disabled, 1= enabled) – CFG3..CFG0 = PWM 0-3 Output (0 = Open Drain Push-Pull) – CFG4 = PWM 4 Output (0 = Open Drain Push-Pull) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Bit Register Name ...

Page 76

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Programmable Period 8-bit PWM The PWM 4 channel can be programmed to pro- vide a PWM output with variable pulse width and period. The PWM 4 has a 16-bit Prescaler bit Counter, a Pulse Width Register, and a Period Register. The Pulse Width Register defines the Figure 37 ...

Page 77

... Comparator Registers and are compared to the Figure 38. PWM 4 With Programmable Pulse Width and Frequency PWM4 Defined by Pulse UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Counter output. When the content of the counter is equal to or greater than the value in the Pulse Width Register, it sets the PWM 4 output to low (with PWMP Bit = 0) ...

Page 78

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV INTERFACE 2 There are two serial I C ports implemented in the uPSD323X Devices. The serial port supports the twin line I sists of a data line (SDAx) and a clock line (SCLx). Depending on the configuration, the SDA and SCL lines may require pull-up resistors. ...

Page 79

... These two bits along with the CR2 Bit determine the serial clock frequency when SIO is in the Master Mode. 0 CR0 Table 52. Selection of the Serial Clock Frequency SCL in Master Mode CR2 CR1 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV STA STO ADDR CR0 f Divisor OSC 12MHz 0 16 375 1 24 250 0 30 200 1 60 ...

Page 80

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Serial Status Register (SxSTA: S1STA, S2STA) SxSTA is a “Read-only” register. The contents of this register may be used as a vector to a service routine. This optimized the response time of the software and consequently that of the I The status codes for all possible modes of the I bus interface are given Table 54 ...

Page 81

... OSC 30MHz (f /2 -> 66.6ns) OSC 20MHz (f /2 -> 100ns) OSC 8MHz (f /2 -> 250ns) OSC UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 2 the I to work with the large range of MCU frequency val- ues supported. For example, with a system clock of 40MHz SLA4 SLA3 SLA2 ...

Page 82

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDC INTERFACE The basic DDC unit consists and 256 bytes of SRAM for DDC data storage. The 8032 core is responsible of loading the contents of the SRAM with the DDC data. The DDC unit has the following features: Supports both DDC1 and DDC2b Modes. ...

Page 83

... D4 RAMBUF D5 DDCDAT D6 DDCADR D7 DDCCON — EX_DAT SWENB DDC_AX DDCINT DDC1EN SWHINT UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDCADR Register. Address pointer for DDC in- terface (DDCADR: 0D6H) 8-bit READ and WRITE register Inter- Address pointer with the capability of the post increment. After each access to RAMBUF ...

Page 84

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 61. Description of the DDCON Register Bits Bit Symbol 7 — Reserved 0 = The SRAM has 128 bytes (Default) 6 EX_DAT 1 = The SRAM has 256 bytes Note: This bit is valid for DDC1 & DDC2b Modes 0 = Data is automatically read from SRAM at the current location of DDCADR and sent ...

Page 85

... No MCU interrupt and no DDC activity will occur. MCU can access DDC SRAM: data space FF00h- FFFFh is dedicated to DDC SRAM. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDCCON.bit2 = 1 (DDC1 Mode Enable Mode Disable) In this state, the DDC is enabled and the unit is in automatic mode. The DDC SRAM cannot be accessed by the MCU – ...

Page 86

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Host Type Detection The detection procedure conforms to the se- quences proposed by VESA Monitor Display Data Channel (DDC) specification. The monitor needs to determine the type of host system: Figure 41. Host Type Detection Power on 86/175 DDC1 or OLD type host. DDC2B host (Host is master, monitor is always slave) DDC2B+/DDC2AB(ACCESS ...

Page 87

... VCLK 1 2 DDC1INT DDC1EN SD t SU(DDC1) t H(VCLK) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The maximum V (40µs). And the 9th clock of V rupt period. CLK So the machine cycle be needed is calculated as below. For example, When 40MHz system clock, 40µs = 133 x (25ns x 12); 133 machine cycle. ...

Page 88

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DDC2B Protocol DDC2B is constructed based on the Philips I terface. However, in the level of DDC2B, PC host is fixed as the master and the monitor is always re- garded as the slave. Both master and slave can be operated as a transmitter or receiver, but the mas- ter device determines which mode is activated. In this protocol, address pointer is also used ...

Page 89

... USBEN UADD6 UADD0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ery circuit recovers the clock from the incoming USB data stream and is able to track jitter and fre- quency drift according to the USB specification. The SIE also translates the electrical USB signals into bytes or signals. Depending upon the device USB address and the USB endpoint ...

Page 90

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 65. USB Interrupt Enable Register (UIEN: 0E9h SUSPNDI RSTE RSTFIE Table 66. Description of the UIEN Bits Bit Symbol 7 SUSPNDI 6 RSTE 5 RSTFIE 4 TXD0IE 3 RXD0IE 2 TXD1IE 1 EOPIE 0 RESUMI Table 67. USB Interrupt Status Register (UISTA: 0E8h SUSPND — 90/175 TXD0IE RXD0IE ...

Page 91

... TXD1F 1 EOPF 0 RESUMF UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV R/W USB Suspend Mode Flag. To save power, this bit should be set if a 3ms constant idle state is detected on USB bus. Setting this bit stops the clock to the USB and R/W causes the USB module to enter Suspend Mode. Software must clear ...

Page 92

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 69. USB Endpoint0 Transmit Control Register (UCON0: 0EAh TSEQ0 STALL0 Table 70. Description of the UCON0 Bits Bit Symbol 7 TSEQ0 6 STALL0 5 TX0E 4 RX0E TP0SIZ3 TP0SIZ0 92/175 TX0E RX0E TP0SIZ3 R/W Endpoint0 Data Sequence Bit. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be R/W sent during the next IN transaction ...

Page 93

... TSEQ1 6 EP12SEL 5 TX1E 4 FRESUM TP1SIZ3 TP1SIZ0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV TX1E FRESUM TP1SIZ3 R/W Endpoint 1/ Endpoint 2 Transmit Data Packet PID. (0=DATA0, 1=DATA1) This bit determines which type of data packet (DATA0 or DATA1) will be R/W sent during the next IN transaction directed to Endpoint 1 or Endpoint 2. ...

Page 94

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 73. USB Control Register (UCON2: 0ECh — — Table 74. Description of the UCON2 Bits Bit Symbol — 4 SOUT 3 EP2E 2 EP1E 1 STALL2 0 STALL1 Table 75. USB Endpoint0 Status Register (USTA: 0EDh RSEQ SETUP Table 76. Description of the USTA Bits Bit Symbol ...

Page 95

... UADR USBEN UADD6 EF UDR0 UDR0.7 UDR0.6 UDR0.5 UDR0.4 UDR0.3 UDR0.2 UDR0.1 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Note: USB works ONLY with the MCU Clock fre- quencies of 12, 24, or 36MHz. The Prescaler val- ues for these frequencies are 0, 1, and 2. Bit Register Name UDT1 ...

Page 96

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Transceiver USB Physical Layer Characteristics. The lowing section describes the uPSD323X Devices compliance to the Chapter 7 Electrical section of the USB Specification, Revision 1.1. The section contains all signaling, and physical layer specifica- tions necessary to describe a low speed USB function ...

Page 97

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV tolerates static input voltages between -0.5V to 3.8V with respect to its local ground reference without damage. In addition to the differential re- ceiver, there is a single-ended receiver for each of the two data lines. The single-ended receivers have a switching threshold between 0 ...

Page 98

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV External USB Pull-Up Resistor The USB system specifies a pull-up resistor on the D- pin for low-speed peripherals. The USB Spec 1.1 describes a 1.5k 3.3V supply. An approved alternative method is a 7.5k pull-up to the USB V CC Figure 46. USB Data Signal Timing and Voltage Levels ...

Page 99

... Figure 48. Differential to EOP Transition Skew and EOP Width T PERIOD Differential Data Lines Figure 49. Differential Data Jitter T PERIOD Differential Data Lines UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Crossover Crossover Point Extended Point Diff. Data to SE0 Skew N*T +T PERIOD DEOP Crossover Points Consecutive Transitions N*T ...

Page 100

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 81. Transceiver DC Characteristics Symb Parameter V Static Output High OH V Static Output Low OL V Differential Input Sensitivity DI V Differential Input Common Mode CM V Single Ended Receiver Threshold SE C Transceiver Capacitance IN I Data Line (D+, D-) Leakage IO External Bus Pull-up Resistance, D- ...

Page 101

... CPLD with 16 Output Micro Cells (OMCs} and 20 Input Micro Cells (IMCs). The CPLD may be used to efficiently implement a variety of logic functions for internal and external control. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Examples include state machines, loadable shift registers, and loadable counters. Decode PLD (DPLD) that decodes address for selection of memory blocks in the PSD Module ...

Page 102

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 50. PSD MODULE Block Diagram 102/175 AI05797 ...

Page 103

... Primary Flash Memory Secondary Flash Memory PLD Array (DPLD and CPLD) PSD MODULE Configuration UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV way by executing out of the primary Flash memo- ry. The PLD or other PSD MODULE Configuration blocks can be programmed through the JTAG port or a device programmer. Table 83 indicates which programming methods can program different func- tional blocks of the PSD MODULE ...

Page 104

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV DEVELOPMENT SYSTEM The uPSD3200 is supported by PSDsoft, a Win- dows-based software development tool (Win- dows-95, Windows-98, Windows-NT). A PSD MODULE design is quickly and easily produced in a point and click environment. The designer does not need to enter Hardware Description Language (HDL) equations, unless desired, to define PSD MODULE pin functions and memory map informa- tion ...

Page 105

... Secondary Flash memory Protection PMMR0 PMMR2 Page VM Note: 1. Other registers that are not part of the I/O ports. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD MODULE registers. Table 84 provides brief descriptions of the registers in CSIOP space. The following section gives a more detailed descrip- tion. (1) Port C ...

Page 106

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD MODULE DETAILED OPERATION As shown in Figure 15, the PSD MODULE con- sists of five major types of functional blocks: Memory Block PLD Blocks I/O Ports Power Management Unit (PMU) JTAG Interface The functions of each block are described in the following sections. Many of the blocks perform multiple functions, and are user configurable ...

Page 107

... Flash memory: Erase memory by chip or sector Suspend or resume sector erase Program a Byte RESET to READ Mode UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Read Sector Protection Status Bypass These instructions are detailed in Table 85. For ef- ficient decoding of the instructions, the first two bytes of an instruction are the coded cycles and ...

Page 108

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 85. Instructions FS0-FS7 or Instruction CSBOOT0- CSBOOT3 (5) 1 READ READ Sector 1 (6,8,13) Protection Program a Flash 1 (13) Byte Flash Sector 1 (7,13) Erase Flash Bulk 1 (13) Erase Suspend Sector 1 (11) Erase Resume Sector 1 (12) Erase (6) 1 RESET Unlock Bypass 1 Unlock Bypass ...

Page 109

... The sector protection status for all NVM blocks (primary Flash memory or secondary Flash mem- ory) can also be read by the MCU accessing the Flash Protection registers in PSD I/O space. See UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV the section entitled “Flash Memory Sector Pro- tect,” page 114, for register definitions. and CSBOOT0- Reading the Erase/Program Status Bits ...

Page 110

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Toggle Flag (DQ6). The Flash memory offers an- other way for determining when the Program cycle is completed. During the internal WRITE operation and when either the FS0-FS7 or CSBOOT0- CSBOOT3 is true, the Toggle Flag Bit (DQ6) tog- gles from '0' to '1' and '1' to '0' on subsequent at- tempts to read any byte of the memory ...

Page 111

... It is suggested (as with all Flash memories) to read the location again after the embedded program- ming algorithm has completed, to compare the UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV byte that was written to the Flash memory with the byte that was intended to be written. When using the Data Polling method during an Erase cycle, Figure 52 still applies ...

Page 112

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Data Toggle. Checking the Toggle Flag Bit (DQ6 method of determining whether a Pro- gram or Erase cycle is in progress or has complet- ed. Figure 53 shows the Data Toggle algorithm. When the MCU issues a Program instruction, the embedded algorithm begins. The MCU then reads the location of the byte to be programmed in Flash memory to check status ...

Page 113

... The UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV input of a new Sector Erase code restarts the time- out period. The status of the internal timer can be monitored through the level of the Erase Time-out Flag Bit (DQ3) ...

Page 114

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV – Reset Flash instruction is received, data in the Flash memory sector that was being erased is invalid. Resume Sector Erase Suspend Sector Erase instruction was previously executed, the erase cycle may be resumed with this instruction. The Resume Sector Erase instruction consists of ...

Page 115

... Voltage Stand- PC2). If you have an STBY external battery connected to the uPSD3200, the UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV contents of the SRAM are retained in the event of a power loss. The contents of the SRAM are re- tained so long as the battery voltage remains greater. If the supply voltage falls below the bat- tery voltage, an internal power switch-over to the battery occurs ...

Page 116

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Example. FS0 is valid when the address is in the range of 8000h to BFFFh, CSBOOT0 is valid from 8000h to 9FFFh, and RS0 is valid from 8000h to 87FFh. Any address in the range of RS0 always accesses the SRAM. Any address in the range of CSBOOT0 greater than 87FFh (and less than 9FFFh) automatically addresses secondary Flash memory segment 0 ...

Page 117

... VM REG BIT 4 PSEN VM REG BIT 1 VM REG BIT 2 VM REG BIT 0 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Combined Space Modes. The Data spaces are combined into one memory space that allows the primary Flash memory, sec- ondary Flash memory, and SRAM to be accessed by either Program Select Enable (PSEN) or READ Strobe (RD) ...

Page 118

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Page Register The 8-bit Page Register increases the addressing capability of the MCU Core by a factor 256. The contents of the register can also be read by the MCU. The outputs of the Page Register (PGR0-PGR7) are inputs to the DPLD decoder and can be included in the Sector Select (FS0- FS7, CSBOOT0-CSBOOT3), and SRAM Select (RS0) equations ...

Page 119

... Flash memory Ready/Busy Program Status Bit Note: 1. These inputs are not available in the 52-pin package. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV The PSD MODULE contains two PLDs: the De- code PLD (DPLD), and the Complex PLD (CPLD). The PLDs are briefly discussed in the next few paragraphs, and in more detail in the section enti- tled “ ...

Page 120

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 58. PLD Diagram 8 PAGE DATA REGISTER BUS DECODE PLD 73 OUTPUT MACROCELL FEEDBACK 16 CPLD 73 DIRECT MACROCELL INPUT TO MCU DATA BUS INPUT MACROCELL & INPUT PORTS 20 2 Note: 1. Ports A is not available in the 52-pin package 120/175 8 PRIMARY FLASH MEMORY SELECTS ...

Page 121

... RESET RD_BSY Note: 1. Port A inputs are not available in the 52-pin package 2. Inputs from the MCU module UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 4 Sector Select (CSBOOT0-CSBOOT3) signals for the secondary Flash memory (three product terms each) 1 internal SRAM Select (RS0) signal (two product terms) ...

Page 122

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Complex PLD (CPLD) The CPLD can be used to implement system logic functions, such as loadable counters and shift reg- isters, system mailboxes, handshaking protocols, state machines, and random logic. The CPLD can also be used to generate External Chip Select (ECS1-ECS2), routed to Port D. ...

Page 123

... Note: 1. McellAB0-McellAB7 can only be assigned to Port B in the 52-pin package. 2. Port PC0, PC1, PC5, and PC6 are assigned to JTAG pins and are not available as Macrocell outputs. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV XOR gate. The Output Macrocell (OMC) can im- plement either sequential logic, using the flip-flop element, or combinatorial logic ...

Page 124

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Product Term Allocator The CPLD has a Product Term Allocator. PSDsoft uses the Product Term Allocator to borrow and place product terms from one macrocell to anoth- er. The following list summarizes how product terms are allocated: McellAB0-McellAB7 all have three native ...

Page 125

... Figure 62. Input Macrocell ENABLE ( . FEEDBACK UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O functions. The internal node feedback can be routed as an input to the AND Array. Input Macrocells (IMC) The CPLD has 20 Input Macrocells (IMC), one for each pin on Ports A and B, and 4 on Port C. The architecture of the Input Macrocells (IMC) is shown in Figure 62 ...

Page 126

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV I/O PORTS (PSD MODULE) There are four programmable I/O ports: Ports and D in the PSD MODULE. Each of the ports is eight bits except Port D, which is 3 bits. Each port pin is individually user configurable, thus al- lowing multiple functions per port. The ports are ...

Page 127

... Register the output enable product term. See the section entitled “Peripheral I/O Mode,” page 127. When the pin is configured as an out- UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV put, the content of the Data Out Register drives the pin. When configured as an input, the MCU can read the port input through the Data In buffer ...

Page 128

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 64. Peripheral I/O Mode RD PSEL0 PSEL1 VM REGISTER BIT 7 WR Table 92. Port Operating Modes Port Mode MCU I/O Yes PLD I/O McellAB Outputs Yes McellBC Outputs No Additional Ext. CS Outputs No PLD Inputs Yes Address Out Yes (A7 – 0) Peripheral I/O ...

Page 129

... A pin can be configured as Open Drain if its corre- sponding bit in the Drive Select Register is set to a '1.' The default pin drive is CMOS. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Note: The slew rate is a measurement of the rise and fall times of an output. A higher slew rate means a faster output response and may create more electrical noise ...

Page 130

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Port Data Registers The Port Data Registers, shown in Table 100, are used by the MCU to write data to or read data from the ports. Table 100 shows the register name, the ports having each register type, and MCU access for each register type ...

Page 131

... DIR REG ENABLE PRODUCT TERM ( .OE ) CPLD-INPUT UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV CPLD Input – Via the Input Macrocells (IMC). Latched Address output – Provide latched address output as per Table 94. Open Drain/Slew Rate – pins PA3-PA0 and PB3-PB0 can be configured to fast slew rate, pins PA7-PA4 and PB7-PB4 can be configured to Open Drain Mode ...

Page 132

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Port C – Functionality and Structure Port C can be configured to perform one or more of the following functions (see Figure 66): MCU I/O Mode CPLD Output – McellBC7-McellBC0 outputs can be connected to Port B or Port C. CPLD Input – via the Input Macrocells (IMC) In-System Programming (ISP) – ...

Page 133

... WR ECS [ 2:1 ] READ MUX DIR REG. WR UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV CPLD Input – direct input to the CPLD, no Input Macrocells (IMC) Slew rate – pins can be set up for fast slew rate Port D pins can be configured in PSDsoft Express as input pins for other dedicated functions: ...

Page 134

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV External Chip Select The CPLD also provides two External Chip Select (ECS1-ECS2) outputs on Port D pins that can be used to select external devices. Each External Chip Select (ECS1-ECS2) consists of one product Figure 68. Port D External Chip Select Signals PT1 PT2 134/175 term that can be configured active High or Low ...

Page 135

... Turbo Mode turned on). While Turbo Mode is off, the PLDs can achieve standby current when no PLD inputs are changing (zero DC cur- UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Power-down Mode, all address/data signals are blocked from reaching memory and PLDs, and the memories are deselected internally. This al- ...

Page 136

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Automatic Power-down (APD) Unit and Power- down Mode. The APD Unit, shown in Figure 69, puts the PSD MODULE into Power-down Mode by monitoring the activity of Address Strobe (ALE). If the APD Unit is enabled, as soon as activity on Ad- dress Strobe (ALE) stops, a four-bit counter starts counting ...

Page 137

... X 0 Bit UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PSD Chip Select Input (CSI, PD2) PD2 of Port D can be configured in PSDsoft Ex- press as PSD Chip Select Input (CSI). When Low, the signal selects and enables the PSD MODULE Flash memory, SRAM, and I/O blocks for READ or WRITE operations ...

Page 138

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 103. Power Management Mode Registers PMMR2 Bit Bit input to the PLD AND Array is connected. PLD Array Bit off WR input to PLD AND Array is disconnected, saving power input to the PLD AND Array is connected. PLD Array Bit off RD input to PLD AND Array is disconnected, saving power. ...

Page 139

... V (min NLNH-PO Power-On Reset RESET UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV before the device is operational after a Warm after V RESET. Figure 71 shows the timing of the Power- NLNH- and Warm RESET. I/O Pin, Register and PLD Status at RESET Table 105 shows the I/O pin, register and PLD sta- tus during Power-on RESET, Warm RESET, and Power-down Mode ...

Page 140

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 105. Status During Power-on RESET, Warm RESET and Power-down Mode Port Configuration MCU I/O Input mode Valid after internal PSD PLD Output configuration bits are loaded Address Out Tri-stated Peripheral I/O Tri-stated Register PMMR0 and PMMR2 ...

Page 141

... TERR PC5 TDI PC6 TDO UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV JTAG Extensions TSTAT and TERR are two JTAG extension signals enabled by an “ISC_ENABLE” command received over the four standard JTAG signals (TMS, TCK, TDI, and TDO). They are used to speed Program ...

Page 142

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV AC/DC PARAMETERS These tables describe the AD and DC parameters of the uPSD323X Devices: DC Electrical Specification AC Timing Specification PLD Timing – Combinatorial Timing – Synchronous Clock Mode – Asynchronous Clock Mode – Input Macrocell Timing MCU Module Timing – READ Timing – ...

Page 143

... I total = 20mA x 40% + 28.45mA x 40% + 250µA x 60% CC This is the operating power with no Flash memory Erase or Program cycles in progress. Calculation is based on all I/ O pins being disconnected and I OUT UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Conditions = 12MHz = 8MHz = 2MHz = 80 (no additional power above base) ...

Page 144

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV MAXIMUM RATING Stressing the device above the rating listed in the Absolute Maximum Ratings” table may cause per- manent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not im- Table 108 ...

Page 145

... V Supply Voltage CC Ambient Operating Temperature (industrial Ambient Operating Temperature (commercial) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ment Conditions summarized in the relevant tables. Designers should check that the operating conditions in their circuit match the measurement conditions when relying on the quoted parame- ters. Parameter Parameter Min ...

Page 146

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 111. AC Symbols for Timing Signal Letters A Address C Clock D Input Data I Instruction L ALE N RESET Input or Output P PSEN signal Q Output Data R RD signal W WR signal B V Output STBY M Output Macrocell Example: t Time from Address Valid to ALE – AVLX Invalid. Figure 74. Switching Waveforms – ...

Page 147

... V LKO Program V SRAM (PSD) Stand-by Voltage STBY SRAM (PSD) Data Retention V DF Voltage Logic '0' Input Current I IL (Ports 1,2,3,4) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Test Condition (in addition to those in Table 109, page 145) 4.5V < V < 5.5V CC 4.5V < V < 5.5V CC 4.5V < V < 5.5V CC 4.5V < V < ...

Page 148

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Symbol Parameter Logic 1-to-0 Transition Current I TL (Ports 1,2,3,4) SRAM (PSD) Stand-by Current I STBY (V input) STBY SRAM (PSD) Idle Current I IDLE (V input) STBY Reset Pin Pull-up Current I RST (RESET) XTAL Feedback Resistor I FR Current (XTAL1) I Input Leakage Current ...

Page 149

... V LKO Program V SRAM (PSD) Stand-by Voltage STBY SRAM (PSD) Data Retention V DF Voltage Logic '0' Input Current I IL (Ports 1,2,3,4) UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Test Condition (in addition to those in Table 110, page 145) 3.0V < V < 3.6V CC 3.0V < V < 3.6V CC 3.0V < V < 3.6V CC 3.0V < V < ...

Page 150

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Symbol Parameter Logic 1-to-0 Transition Current I TL (Ports 1,2,3,4) SRAM (PSD) Stand-by Current I STBY (V input) STBY SRAM (PSD) Idle Current I IDLE (V input) STBY Reset Pin Pull-up Current I RST (RESET) XTAL Feedback Resistor I FR Current (XTAL1) I Input Leakage Current ...

Page 151

... AZPL Note: 1. Conditions (in addition to those in Table 109, V other outputs is 80pF 2. Interfacing the uPSD323X Devices to devices with float times up to 20ns is permissible. This limited bus contention does not cause any damage to Port 0 drivers. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV t LLPL t PLPH t LLIV t PLIV t LLAX ...

Page 152

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 115. External Program Memory AC Characteristics (with the 3V MCU Module) Symbol Parameter t ALE pulse width LHLL t Address set-up to ALE AVLL t Address hold after ALE LLAX t ALE Low to valid instruction in LLIV t ALE to PSEN LLPL t PSEN pulse width PLPH ...

Page 153

... A0-A7 from PORT 0 PORT 2 Figure 77. External Data Memory WRITE Cycle ALE tLHLL PSEN WR tAVLL A0-A7 from PORT DPL PORT 2 UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV tLLDV tLLWL tRLRH tRLDV tLLAX2 tRLAZ DATA DPL tAVWL tAVDV P2.0 to P2.3 or A8-A11 from DPH tLLWL tWLWH ...

Page 154

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 118. External Data Memory AC Characteristics (with the 5V MCU Module) Symbol Parameter t RD pulse width RLRH t WR pulse width WLWH t Address hold after ALE LLAX2 valid data in RHDX t Data hold after RD RHDX t Data float after RD RHDZ t ALE to valid data in ...

Page 155

... N Non-Linearity Error NLE N Differential Non-Linearity Error DNLE N Zero-Offset Error ZOE N Full Scale Error FSE N Gain Error GE T Conversion Time CONV UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 24MHz Oscillator (1) Min 180 180 170 15 = 3.0 to 3.6V 0V for other outputs is 80pF, for 5V devices, and 50pF for 3V devices) ...

Page 156

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 78. Input to Output Disable / Enable INPUT INPUT TO OUTPUT ENABLE/DISABLE Table 121. CPLD Combinatorial Timing (5V Devices) Symbol Parameter CPLD Input Pin/Feedback to ( CPLD Combinatorial Output CPLD Input to CPLD Output t EA Enable CPLD Input to CPLD Output t ER Disable CPLD Register Clear or Preset ...

Page 157

... CL t Clock to Output Delay CO t CPLD Array Delay ARD t Minimum Clock Period MIN Note: 1. Fast Slew Rate output available on PA3-PA0, PB3-PB0, and PD2-PD1. Decrement times by given amount. 2. CLKIN (PD1 CLCL CH CL UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Conditions Min 1/( 1/(t +t –10 1/(t +t ...

Page 158

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 124. CPLD Macrocell Synchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAX Internal Feedback (f CNT Maximum Frequency Pipelined Data t Input Setup Time S t Input Hold Time H t Clock High Time CH t Clock Low Time ...

Page 159

... Input Hold Time HA t Clock Input High Time CHA t Clock Input Low Time CLA t Clock to Output Delay COA t CPLD Array Delay ARDA t Minimum Clock Period MINA UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV tARPW tARP tCHA tCLA tSA Conditions Min 1/( COA 1/(t +t –10) SA COA ...

Page 160

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 126. CPLD Macrocell Asynchronous Clock Mode Timing (3V Devices) Symbol Parameter Maximum Frequency External Feedback Maximum Frequency f MAXA Internal Feedback (f CNTA Maximum Frequency Pipelined Data t Input Setup Time SA t Input Hold Time HA t Clock High Time CHA ...

Page 161

... NIB Input High Time INH t NIB Input Low Time INL t NIB Input to Combinatorial Delay INO Note: 1. Inputs from Port A, B, and C relative to register/latch clock from the PLD. ALE latch timings refer to t UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV t t INH INL Conditions Min ...

Page 162

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Table 129. Program, WRITE and Erase Times (5V Devices) Symbol Flash Program (1) Flash Bulk Erase Flash Bulk Erase (not pre-programmed) t Sector Erase (pre-programmed) WHQV3 t Sector Erase (not pre-programmed) WHQV2 t Byte Program WHQV1 Program / Erase Cycles (per Sector) t Sector Erase Time-Out ...

Page 163

... RLQV–PA t Data In to Data Out Valid DVQV– Data High-Z RHQZ–PA Note: 1. Any input used to select Port A Data Peripheral Mode. 2. Data is already stable on Port A. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV ADDRESS t AVQV ( PA) t SLQV ( PA) t RLQV (PA) Conditions (Note 1) (Note 2) Conditions (Note 1) ...

Page 164

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 84. Peripheral I/O WRITE Timing ALE BUS WR Table 133. Port A Peripheral Data Mode WRITE Timing (5V Devices) Symbol Data Propagation Delay WLQV–PA t Data to Port A Data Propagation Delay DVQV– Invalid to Port A Tri-state WHQZ–PA Note: 1. Data stable on Port 0 pins to data on Port A. ...

Page 165

... STBYON Symbol Parameter t V Detection to V BVBH STBY V Off Detection to V STBY t BXBL Low Note timing is measured at V STBYON UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV t OPR Conditions (1) Conditions (1) Conditions Output High (Note 1) STBYON Output STBYON (Note 1) ramp rate of 2ms. CC Conditions Output High (Note 1) ...

Page 166

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 86. ISC Timing TCK TDI/TMS ISC OUTPUTS/TDO ISC OUTPUTS/TDO Table 139. ISC Timing (5V Devices) Symbol Parameter t Clock (TCK, PC1) Frequency (except for PLD) ISCCF t Clock (TCK, PC1) High Time (except for PLD) ISCCH t Clock (TCK, PC1) Low Time (except for PLD) ...

Page 167

... Note: For timing purposes, a Port pin is considered longer floating when a 100mV change from load voltage occurs, and begins to float when a 100mV change from the loaded V I and I 20mA OL OH UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV 0 0.9V Test Points 0 – 0.1V 0.45V –0.5V for a logic '1,' and 0.45V for a logic '0.' CC ...

Page 168

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 89. External Clock Cycle Figure 90. Recommended Oscillator Circuits Note: C1 30pF ± 10pF for crystals For ceramic resonators, contact resonator manufacturer Oscillation circuit is designed to be used either with a ceramic resonator or crystal oscillator. Since each crystal and ceramic resonator have their own characteristics, the user should consult the crystal manufacturer for appropriate values of external components ...

Page 169

... U = 80-pin TQFP Temperature Range 70° –40 to 85°C Shipping Option Tape & Reel Packing = T For a list of available options (e.g., Speed, Package) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV uPSD – 24 ...

Page 170

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV PACKAGE MECHANICAL INFORMATION Figure 93. TQFP52 – 52-lead Plastic Quad Flatpack Package Outline QFP-A Note: Drawing is not to scale. 170/175 ...

Page 171

... D 12.00 D1 10. 12.00 E1 10. 0.65 L – L1 1.00 – – UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV mm Min Max – 1.75 0.05 0.020 1.25 1.55 0.02 0.04 0.07 0.23 – – – – – – – – – – 0.45 0.75 – ...

Page 172

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV Figure 94. TQFP80 – 80-lead Plastic Quad Flatpack Package Outline QFP-A Note: Drawing is not to scale. 172/175 ...

Page 173

... D 14.00 D1 12.00 D2 9.50 E 14.00 E1 12.00 E2 9.50 e 0.50 L 0.60 L1 1.00 3 – UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV mm Min Max – 1.60 0.05 0.15 1.35 1.45 0.17 0.27 0.09 0.20 – – – – – – – – – – – – – ...

Page 174

... UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV REVISION HISTORY Table 145. Document Revision History Date Rev. # November 2002 1.0 First Issue Updates: product information (Figure 3, 4, Table 1, 2); port information (Figure 17, 18, Table 30); interface information (Figure 30, Table 44); remove programming guide; PSD 27-Feb-03 1.1 Module information (Figure 50, 51, Table 85); PLD information (Figure 58, 59, Table 91, 92, 93) ...

Page 175

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States UPSD3234A, UPSD3234BV, UPSD3233B, UPSD3233BV All other names are the property of their respective owners © 2003 STMicroelectronics - All rights reserved STMicroelectronics GROUP OF COMPANIES www ...

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