N80C196KC20 Intel, N80C196KC20 Datasheet - Page 8

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N80C196KC20

Manufacturer Part Number
N80C196KC20
Description
IC MPU 16BIT 5V 20MHZ 68PLCC
Manufacturer
Intel
Series
80Cr
Datasheet

Specifications of N80C196KC20

Rohs Status
RoHS non-compliant
Core Processor
MCS 96
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO
Peripherals
PWM, WDT
Number Of I /o
48
Program Memory Type
ROMless
Ram Size
488 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
68-PLCC
Eeprom Size
-
Program Memory Size
-
Other names
804097

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8XC196KC 8XC196KC20
PIN DESCRIPTIONS
8
Ports 3 and 4
HOLD
HLDA
BREQ
PMODE
PACT
CPVER
PALE
PROG
PVER
AINC
Symbol
8-bit bidirectional I O ports with open drain outputs These pins are shared with the
multiplexed address data bus which has strong internal pullups
Bus Hold input requesting control of the bus
Bus Hold acknowledge output indicating release of the bus
Bus Request output activated when the bus controller has a pending external memory
cycle
Determines the EPROM programming mode
A low signal in Auto Programming mode indicates that programming is in process A high
signal indicates programming is complete
Cummulative Program Output Verification Pin is high if all locations have programmed
correctly since entering a programming mode
A falling edge in Slave Programming Mode and Auto Configuration Byte Programming Mode
indicates that ports 3 and 4 contain valid programming address command information
(input to slave)
A falling edge in Slave Programming Mode indicates that ports 3 and 4 contain valid
programming data (input to slave)
A high signal in Slave Programmig Mode and Auto Configuration Byte Programming Mode
indicates the byte programmed correctly
Auto Increment Active low input signal indicates that the auto increment mode is enabled
Auto Increment will allow reading or writing of sequential EPROM locations without address
transactions across the PBUS for each read or write
(Continued)
Name and Function

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