MC68HC705P6ACDW Freescale Semiconductor, MC68HC705P6ACDW Datasheet - Page 69
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MC68HC705P6ACDW
Manufacturer Part Number
MC68HC705P6ACDW
Description
IC MCU 2.1MHZ 4.5K OTP 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC705P6ACDWE.pdf
(98 pages)
Specifications of MC68HC705P6ACDW
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SIO
Peripherals
POR, WDT
Number Of I /o
21
Program Memory Size
4.5KB (4.5K x 8)
Program Memory Type
OTP
Ram Size
176 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Data Bus Width
8 bit
Data Ram Size
176 B
Maximum Clock Frequency
2.1 MHz
Number Of Programmable I/os
37
Number Of Timers
16 bit
Operating Supply Voltage
3.3 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No RoHS Version Available
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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Manufacturer:
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1 143
I — Interrupt Mask Bit
N — Negative Bit
Z — Zero Bit
C — Carry/Borrow Bit
Freescale Semiconductor
When the interrupt mask is set, the internal and external interrupts are disabled. Interrupts are enabled
when the interrupt mask is cleared. When an interrupt occurs, the interrupt mask is automatically set
after the CPU registers are saved on the stack, but before the interrupt vector is fetched. If an interrupt
request occurs while the interrupt mask is set, the interrupt request is latched. Normally, the interrupt
is processed as soon as the interrupt mask is cleared.
A return from interrupt (RTI) instruction pulls the CPU registers from the stack, restoring the interrupt
mask to its state before the interrupt was encountered. After any reset, the interrupt mask is set and
can only be cleared by the clear I bit (CLI), STOP, or WAIT instructions.
The negative bit is set when the result of the last arithmetic operation, logical operation, or data
manipulation was negative. (Bit 7 of the result was a logic one.)
The negative bit can also be used to check an often-tested flag by assigning the flag to bit 7 of a
register or memory location. Loading the accumulator with the contents of that register or location then
sets or clears the negative bit according to the state of the flag.
The zero bit is set when the result of the last arithmetic operation, logical operation, data manipulation,
or data load operation was zero.
The carry/borrow bit is set when a carry out of bit 7 of the accumulator occurred during the last
arithmetic operation, logical operation, or data manipulation. The carry/borrow bit is also set or cleared
during bit test and branch instructions and during shifts and rotates. This bit is not set by an INC or
DEC instruction.
MC68HC705P6A Advance Information Data Sheet, Rev. 2.1
Registers
69