MCF5307FT90B Freescale Semiconductor, MCF5307FT90B Datasheet - Page 378
MCF5307FT90B
Manufacturer Part Number
MCF5307FT90B
Description
IC MPU 32BIT COLDF 90MHZ 208FQFP
Manufacturer
Freescale Semiconductor
Series
MCF530xr
Datasheets
1.MCF5307AI66B.pdf
(484 pages)
2.MCF5307AI66B.pdf
(16 pages)
3.MCF5307AI66B.pdf
(2 pages)
Specifications of MCF5307FT90B
Core Processor
Coldfire V3
Core Size
32-Bit
Speed
90MHz
Connectivity
EBI/EMI, I²C, UART/USART
Peripherals
DMA, POR, WDT
Number Of I /o
16
Program Memory Type
ROMless
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
0°C ~ 70°C
Package / Case
208-FQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
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Clock and Reset Signals
17.5.5.1 D[7:5Boot Chip-Select (CS0) Configuration
D[7:5] determine defaults for the global chip select (CS0), the only chip select valid at reset.
These signals correspond to bits in chip-select configuration register 0 (CSCR0).
17.5.5.2 D7—Auto Acknowledge Configuration (AA_CONFIG)
At reset, the enabling and disabling of auto acknowledge for boot CS0 is determined by the
logic level driven on D7 at the rising edge of RSTI. AA_CONFIG is multiplexed with D7
and sampled only at reset. The D7 logic level is reflected as the reset value of CSCR[AA].
Table 17-12 shows how the D7 logic level corresponds to the auto acknowledge timing for
CS0 at reset. Note that auto acknowledge can be disabled by driving a logic 0 on D7 at reset.
17.5.5.3 D[6:5]—Port Size Configuration (PS_CONFIG[1:0])
The default port size value of the boot CS0 is determined by the logic levels driven on
D[6:5] at the rising edge of RSTI, which are reflected as the reset value of CSCR[PS]. Table
17-13 shows how the logic levels of D[6:5] correspond to the CS0 port size at reset.
17.5.6 D4—Address Configuration (ADDR_CONFIG)
The address configuration signal (ADDR_CONFIG) programs the PAR of the parallel I/O
port to be either parallel I/O or to be the upper address bus bits along with various attribute
and control signals at reset to give the user the option to access a broader addressing range
17-14
Table 17-12. D7 Selection of CS0 Automatic Acknowledge
Table 17-13. D6 and D5 Selection of CS0 Port Size
D[6:5]
D[3:2]
D[1:0]
Pin
D7
D4
D7 (CSCR0[AA])
Freescale Semiconductor, Inc.
Auto-acknowledge configuration (AA_CONFIG)
Port size configuration (PS_CONFIG[1:0])
Address configuration (ADDR_CONFIG/D4)
Frequency Control PLL (FREQ[1:0])
Divide Control (DIVIDE[1:0])
Table 17-11. Data Pin Configuration
For More Information On This Product,
D[6:5] (CSCR0[PS])
0
1
00
01
1x
Go to: www.freescale.com
MCF5307 User’s Manual
Disabled
Enabled with 15 wait states
Function
Boot CS0 Port Size
Boot CS0 AA
32-bit port
16-bit port
8-bit port
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