MC68HC908GZ8VFA Freescale Semiconductor, MC68HC908GZ8VFA Datasheet - Page 247

• Manufacturer Part Number: MC68HC908GZ8VFA
• Description: IC MCU 8K FLASH 8MHZ CAN 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908GZ8VFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: CAN, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

The CPU can always read the state of the SS pin by configuring the appropriate pin as an input and
reading the port data register. See
17.12.5 CGND (Clock Ground)
CGND is the ground return for the serial clock pin, SPSCK, and the ground for the port output buffers. It
is internally connected to V
17.13 I/O Registers
Three registers control and monitor SPI operation:
17.13.1 SPI Control Register
The SPI control register:
SPRIE — SPI Receiver Interrupt Enable Bit
Freescale Semiconductor
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This read/write bit enables CPU interrupt requests generated by the SPRF bit. The SPRF bit is set
when a byte transfers from the shift register to the receive data register. Reset clears the SPRIE bit.
1 = SPRF CPU interrupt requests enabled
0 = SPRF CPU interrupt requests disabled
SPI control register (SPCR)
SPI status and control register (SPSCR)
SPI data register (SPDR)
Enables SPI module interrupt requests
Configures the SPI module as master or slave
Selects serial clock polarity and phase
Configures the SPSCK, MOSI, and MISO pins as open-drain outputs
Enables the SPI module
Address: $0010
1. X = Don’t care
SPE
Reset:
0
1
1
1
Read:
Write:
SPMSTR
SPRIE
Bit 7
X
R
0
(1))
0
1
1
SS
MC68HC908GZ16 • MC68HC908GZ8 Data Sheet, Rev. 4
Figure 17-14. SPI Control Register (SPCR)
as shown in
= Reserved
R
6
0
MODFEN
Table
Table 17-3. SPI Configuration
X
X
0
1
SPMSTR
17-3.
5
1
Table
Master without MODF
SPI Configuration
Master with MODF
17-1.
CPOL
Not enabled
4
0
Slave
CPHA
3
1
SPWOM
2
0
General-purpose I/O;
General-purpose I/O;
State of SS Logic
SS ignored by SPI
SS ignored by SPI
Input-only to SPI
Input-only to SPI
SPE
1
0
SPTIE
Bit 0
0
I/O Registers
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