MC68HC908MR8CFA Freescale Semiconductor, MC68HC908MR8CFA Datasheet - Page 233

• Manufacturer Part Number: MC68HC908MR8CFA
• Description: IC MCU 8K FLASH 8MHZ PWM 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC68HC908MR8CFA

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 16
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

12.4.4.2 Buffered PWM Signal Generation
MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
NOTE:
Use these methods to synchronize unbuffered changes in the PWM
pulse width on channel x:
In PWM signal generation, do not program the PWM channel to toggle
on output compare. Toggling on output compare prevents reliable
0 percent duty cycle generation and removes the ability of the channel
to self-correct in the event of software error or noise. Toggling on output
compare also can cause incorrect PWM signal generation when
changing the PWM pulse width to a new, much larger value.
Channels 0 and 1 can be linked to form a buffered PWM channel whose
output appears on the PTB5/TCH0B pin. The TIMB channel registers of
the linked pair alternately control the pulse width of the output.
Setting the MS0B bit in TIMB channel 0 status and control register
(TBSC0) links channel 0 and channel 1. The TIMB channel 0 registers
initially control the pulse width on the PTB5/TCH0B pin. Writing to the
TIMB channel 1 registers enables the TIMB channel 1 registers to
synchronously control the pulse width at the beginning of the next PWM
period. At each subsequent overflow, the TIMB channel registers (0 or
1) that control the pulse width are the ones written to last. TBSC0
controls and monitors the buffered PWM function, and TIMB channel 1
status and control register (TBSC1) is unused. While the MS0B bit is set,
the channel 1 pin, PTB6/TCH1B, is available as a general-purpose I/O
pin.
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•
When changing to a shorter pulse width, enable channel x output
compare interrupts and write the new value in the output compare
interrupt routine. The output compare interrupt occurs at the end
of the current pulse. The interrupt routine has until the end of the
PWM period to write the new value.
When changing to a longer pulse width, enable TIMB overflow
interrupts and write the new value in the TIMB overflow interrupt
routine. The TIMB overflow interrupt occurs at the end of the
current PWM period. Writing a larger value in an output compare
interrupt routine (at the end of the current pulse) could cause two
output compares to occur in the same PWM period.
Timer Interface B (TIMB)
Timer Interface B (TIMB)
Functional Description
Technical Data
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