C8051F124 Silicon Laboratories Inc, C8051F124 Datasheet - Page 249

• Manufacturer Part Number: C8051F124
• Description: IC 8051 MCU 128K FLASH 100TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F12xr

Specifications of C8051F124

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 64
• Program Memory Size: 128KB (128K x 8)
• Program Memory Type: FLASH
• Ram Size: 8.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 8x8b, 8x12b; D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

Bits7–0: P1.[7:0]: Port1 Output Latch Bits.
Bits7–0: P1MDIN.[7:0]: Port 1 Input Mode Bits.
Notes:
P1.7
R/W
R/W
Bit7
Bit7
1. On C8051F12x devices, P1.[7:0] can be configured as inputs to ADC2 as AIN2.[7:0], in which
2. P1.[7:0] can be driven by the External Data Memory Interface (as Address[15:8] in Non-
(Write - Output appears on I/O pins per XBR0, XBR1, and XBR2 Registers)
0: Logic Low Output.
1: Logic High Output (open if corresponding P1MDOUT.n bit = 0).
(Read - Regardless of XBR0, XBR1, and XBR2 Register settings).
0: P1.n pin is logic low.
1: P1.n pin is logic high.
0: Port Pin is configured in Analog Input mode. The digital input path is disabled (a read from
the Port bit will always return ‘0’). The weak pullup on the pin is disabled.
1: Port Pin is configured in Digital Input mode. A read from the Port bit will return the logic
level at the Pin. When configured as a digital input, the state of the weak pullup for the port
pin is determined by the WEAKPUD bit (XBR2.7, see SFR Definition 18.3).
case they are ‘skipped’ by the Crossbar assignment process and their digital input paths are
disabled, depending on P1MDIN (See SFR Definition 18.7 ) . Note that in analog mode, the
output mode of the pin is determined by the Port 1 latch and P1MDOUT (SFR Definition 18.8).
See
about ADC2.
multiplexed mode). See
XRAM” on page 219
Section “7. ADC2 (8-Bit ADC, C8051F12x Only)” on page 91
P1.6
R/W
R/W
Bit6
Bit6
SFR Definition 18.7. P1MDIN: Port1 Input Mode
P1.5
R/W
R/W
Bit5
Bit5
SFR Definition 18.6. P1: Port1 Data
for more information about the External Memory Interface.
Section “17. External Data Memory Interface and On-Chip
P1.4
R/W
R/W
Bit4
Bit4
Rev. 1.4
P1.3
R/W
R/W
Bit3
Bit3
C8051F120/1/2/3/4/5/6/7
P1.2
R/W
R/W
Bit2
Bit2
C8051F130/1/2/3
P1.1
R/W
R/W
Bit1
Bit1
SFR Address:
for more information
SFR Address:
SFR Page:
SFR Page:
P1.0
R/W
Bit0
R/W
Bit0
0x90
All Pages
Addressable
Reset Value
0xAD
F
11111111
Reset Value
11111111
Bit
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