C8051F330 Silicon Laboratories Inc, C8051F330 Datasheet - Page 65
![no-image](/images/manufacturer_photos/0/6/609/silicon_laboratories_inc_sml.jpg)
C8051F330
Manufacturer Part Number
C8051F330
Description
IC 8051 MCU 8K FLASH 20MLP
Manufacturer
Silicon Laboratories Inc
Series
C8051F33xr
Datasheet
1.C8051F330R.pdf
(208 pages)
Specifications of C8051F330
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F330
Manufacturer:
SILICON
Quantity:
359
Part Number:
C8051F330
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F330-GM
Manufacturer:
SiliconL
Quantity:
6 420
Company:
Part Number:
C8051F330-GM
Manufacturer:
SILICON
Quantity:
121
Part Number:
C8051F330-GM
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F330-GM-15T
Manufacturer:
SILICON
Quantity:
3 741
Part Number:
C8051F330-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Company:
Part Number:
C8051F330GM
Manufacturer:
SILLAB
Quantity:
4 419
9.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
four 16-bit counter/timers (see description in
in
Special Function Register (SFR) address space
tion
directly with the analog and digital subsystems providing a complete data acquisition or control-system
solution in a single integrated circuit.
The CIP-51 Microcontroller core implements the standard 8051 organization and peripherals as well as
additional custom peripherals and functions to extend its capability (see Figure 9.1 for a block diagram).
The CIP-51 includes the following features:
-
-
-
-
-
Performance
The CIP-51 employs a pipelined architecture that greatly increases its instruction throughput over the stan-
dard 8051 architecture. In a standard 8051, all instructions except for MUL and DIV take 12 or 24 system
clock cycles to execute, and usually have a maximum system clock of 12 MHz. By contrast, the CIP-51
core executes 70% of its instructions in one or two system clock cycles, with no instructions taking more
than eight system clock cycles.
Section
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
17 Port I/O
14). The CIP-51 also includes on-chip debug hardware (see description in
CIP-51 Microcontroller
16), an Enhanced SPI (see description in
RESET
CLOCK
STOP
IDLE
ACCUMULATOR
Figure 9.1. CIP-51 Block Diagram
PROGRAM COUNTER (PC)
CONTROL
PSW
PRGM. ADDRESS REG.
LOGIC
POWER CONTROL
PC INCREMENTER
DATA POINTER
REGISTER
BUFFER
TMP1
PIPELINE
Section
ALU
(Section
C8051F330/1, C8051F330D
Rev. 1.2
TMP2
DATA BUS
DATA BUS
D8
D8
D8
18), an enhanced full-duplex UART (see description
-
-
-
-
-
Section
A16
D8
D8
D8
D8
B REGISTER
9.2.6), and 17 Port I/O (see description in
REGISTER
INTERFACE
INTERFACE
INTERRUPT
INTERFACE
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
ADDRESS
MEMORY
SRAM
SFR
BUS
17), 256 bytes of internal RAM, 128 byte
MEM_WRITE_DATA
SFR_WRITE_DATA
MEM_READ_DATA
STACK POINTER
(256 X 8)
SFR_READ_DATA
SRAM
MEM_CONTROL
EMULATION_IRQ
MEM_ADDRESS
SFR_CONTROL
SFR_ADDRESS
SYSTEM_IRQs
Section
20), and interfaces
Sec-
65