C8051F061 Silicon Laboratories Inc, C8051F061 Datasheet - Page 268
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C8051F061
Manufacturer Part Number
C8051F061
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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The baud rate generated in Mode 1 is a function of timer overflow. UART0 can use Timer 1 operating in 8-
Bit Auto-Reload Mode, or Timer 2, 3, or 4 operating in Auto-reload Mode to generate the baud rate (note
that the TX and RX clocks are selected separately). On each timer overflow event (a rollover from all ones
- (0xFF for Timer 1, 0xFFFF for Timer 2, 3, or 4) - to zero) a clock is sent to the baud rate logic.
Timers 1, 2, 3, or 4 are selected as the baud rate source with bits in the SSTA0 register (see Figure 22.9).
The transmit baud rate clock is selected using the S0TCLK1 and S0TCLK0 bits, and the receive baud rate
clock is selected using the S0RCLK1 and S0RCLK0 bits.
When Timer 1 is selected as a baud rate source, the SMOD0 bit (SSTA0.4) selects whether or not to divide
the Timer 1 overflow rate by two. On reset, the SMOD0 bit is logic 0, thus selecting the lower speed baud
rate by default. The SMOD0 bit affects the baud rate generated by Timer 1 as shown in Equation 22.1.
The Timer 1 overflow rate is determined by the Timer 1 clock source (T1CLK) and reload value (TH1). The
frequency of T1CLK is selected as described in
Timer 1 overflow rate is calculated as shown in Equation 22.2.
When Timers 2, 3, or 4 are selected as a baud rate source, the baud rate is generated as shown in
Equation 22.3.
The overflow rate for Timer 2, 3, or 4 is determined by the clock source for the timer (TnCLK) and the 16-
bit reload value stored in the RCAPn register (n = 2, 3, or 4), as shown in Equation 22.4.
268
When SMOD0 = 0:
When SMOD0 = 1:
Timer234_OverflowRate
Mode1_BaudRate
Mode1_BaudRate
Mode1_BaudRate
Equation 22.3. Mode 1 Baud Rate using Timer 2, 3, or 4
Timer1_OverflowRate
Equation 22.1. Mode 1 Baud Rate using Timer 1
Equation 22.4. Timer 2, 3, or 4 Overflow Rate
Equation 22.2. Timer 1 Overflow Rate
=
=
=
1 16
1 32
1 16
Rev. 1.2
Section “24.1. Timer 0 and Timer 1” on page
=
=
TnCLK
T1CLK
Timer234_OverflowRate
Timer1_OverflowRate
Timer1_OverflowRate
65536 RCAPn
256 TH1
–
–
287. The
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