C8051F061 Silicon Laboratories Inc, C8051F061 Datasheet - Page 296
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C8051F061
Manufacturer Part Number
C8051F061
Description
IC 8051 MCU 64K FLASH 64TQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F06xr
Specifications of C8051F061
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
CAN, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
Number Of I /o
24
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 2x16b, 8x10b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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C8051F060/1/2/3/4/5/6/7
24.2.2. Capture Mode
In Capture Mode, Timer 2, 3, and 4 will operate as a 16-bit counter/timer with capture facility. When the
Timer External Enable bit (found in the TMRnCN register) is set to ‘1’, a high-to-low transition on the TnEX
input pin causes the 16-bit value in the associated timer (THn, TLn) to be loaded into the capture registers
(RCAPnH, RCAPnL). If a capture is triggered in the counter/timer, the Timer External Flag (TMRnCN.6)
will be set to ‘1’ and an interrupt will occur if the interrupt is enabled. See
on page 151
As the 16-bit timer register increments and overflows TMRnH:TMRnL, the TFn Timer Overflow/Underflow
Flag (TMRnCN.7) is set to ‘1’ and an interrupt will occur if the interrupt is enabled. The timer can be config-
ured to count down by setting the Decrement Enable Bit (TMRnCF.0) to ‘1’. This will cause the timer to
decrement with every timer clock/count event and underflow when the timer transitions from 0x0000 to
0xFFFF. Just as in overflows, the Overflow/Underflow Flag (TFn) will be set to ‘1’, and an interrupt will
occur if enabled.
Counter/Timer with Capture mode is selected by setting the Capture/Reload Select bit CP/RLn
(TMRnCN.0) and the Timer 2, 3, and 4 Run Control bit TRn (TnCON.2) to logic 1. The Timer 2, 3, and 4
respective External Enable EXENn (TnCON.3) must also be set to logic 1 to enable a captures. If EXENn
is cleared, transitions on TnEX will be ignored.
296
External Clock
SYSCLK
(XTAL1)
Tn
TnEX
for further information concerning the configuration of interrupt sources.
Crossbar
8
2
12
Crossbar
EXENn
Figure 24.11. T2, 3, and 4 Capture Mode Block Diagram
TRn
0
1
TMRnCF
Capture
M
T
n
1
M
T
n
0
T
O
G
n
O
E
T
n
Rev. 1.2
TCLK
D
C
N
E
RCAPnL
TMRnL
0xFF
RCAPnH
TMRnH
0xFF
OVF
Toggle Logic
Section “13.3. Interrupt Handler”
CP/RLn
EXENn
EXFn
C/Tn
TRn
TFn
0
1
Interrupt
(Port Pin)
Tn
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