MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 82

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

5.6.30.4
This bit allows all interrupts to be disabled.
5.6.30.5
This bit field is reserved or not implemented. It is read as 1 and cannot be modified by writing.
5.6.30.6
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.7
This read-only bit reflects the state of the external IRQA pin.
5.6.30.8
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
5.6.30.9
This bit controls whether the external IRQA interrupt is edge- or level-sensitive. During Stop and Wait
modes, it is automatically level-sensitive.
5.7 Resets
5.7.1
The ITCN provides the 56800E core with a reset vector address whenever RESET is asserted. The reset
vector will be presented until the second rising clock edge after RESET is released.
5.7.2
After reset, all of the ITCN registers are in their default states. This means all interrupts are disabled except
the core IRQs with fixed priorities
These interrupts are enabled at their fixed priority levels.
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0 = Normal operation (default)
1 = All interrupts disabled
0 = IRQA interrupt is a low-level sensitive (default)
1 = IRQA interrupt is falling-edge sensitive
Illegal Instruction
SW Interrupt 3
HW Stack Overflow
Misaligned Long Word Access
SW Interrupt 2
SW Interrupt 1
SW Interrupt 0
SW Interrupt LP
Reset Handshake Timing
ITCN After Reset
Interrupt Disable (INT_DIS)—Bit 5
Reserved—Bit 4
Reserved—Bit 3
IRQA State Pin (IRQA STATE)—Bit 2
Reserved—Bit 1
IRQA Edge Pin (IRQA Edg)—Bit 0
56F8323 Technical Data, Rev. 17
Freescale Semiconductor
Preliminary