MC56F8323VFB60 Freescale Semiconductor, MC56F8323VFB60 Datasheet - Page 89

• Manufacturer Part Number: MC56F8323VFB60
• Description: IC MPU HYBRID DSP 32K 64-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8323VFB60

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 60MHz
• Connectivity: CAN, SCI, SPI
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 27
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 12K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 64-LQFP
• For Use With: MC56F8323EVME - BOARD EVALUATION MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

6.5.5
This read-only register displays the least significant half of the JTAG ID for the chip. This register reads
$001D.
6.5.6
Most of the pins on the chip have on-chip pull-up resistors. Pins which can operate as GPIO can have these
resistors disabled via the GPIO function. Non-GPIO pins can have their pull-ups disabled by setting the
appropriate bit in this register. Disabling pull-ups is done on a peripheral-by-peripheral basis (for pins not
muxed with GPIO). Each bit in the register (see
Table 2-2
6.5.6.1
This bit field is reserved or not implemented. It is read as 0 and cannot be modified by writing.
6.5.6.2
This bit controls the pull-up resistors on the RESET pin.
Freescale Semiconductor
Preliminary
Base + $8
RESET
Base + $6
Base + $7
Read
Write
RESET
RESET
Read
Write
Read
Write
to identify which pins can deactivate the internal pull-up resistor.
Least Significant Half of JTAG ID (SIM_LSH_ID)
SIM Pull-up Disable Register (SIM_PUDR)
Reserved—Bits 15–12
RESET—Bit 11
15
0
0
15
15
Figure 6-6 Most Significant Half of JTAG ID (SIM_MSH_ID)
Figure 6-7 Least Significant Half of JTAG ID (SIM_LSH_ID)
0
0
0
0
14
0
0
Figure 6-8 SIM Pull-up Disable Register (SIM_PUDR)
14
14
0
0
1
0
13
0
0
13
13
0
0
0
0
12
0
0
12
12
0
0
0
0
RESET
11
0
56F8323 Technical Data, Rev. 17
11
11
0
0
0
0
IRQ
10
0
10
10
0
0
0
0
Figure
9
0
0
9
0
0
9
0
0
8
0
0
6-8) corresponds to a functional group of pins. See
8
8
1
1
0
0
7
0
0
7
7
1
1
0
0
6
0
0
6
6
1
1
0
0
5
0
0
5
1
1
5
0
0
4
0
0
4
1
1
4
1
1
JTAG
3
0
3
3
0
0
1
1
2
0
0
2
1
1
2
1
1
Register Descriptions
1
0
0
1
0
0
1
0
0
0
0
0
0
0
0
0
1
1
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