XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 252

• Manufacturer Part Number: XC68HC705B32CB
• Description: IC MCU 2.1MHZ 32K OTP 56-DIP
• Manufacturer: Freescale Semiconductor
• Series: HC05r

Specifications of XC68HC705B32CB

• Core Processor: HC05
• Core Size: 8-Bit
• Speed: 2.1MHz
• Connectivity: SCI
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: OTP
• Eeprom Size: 256 x 8
• Ram Size: 528 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 8x8b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 56-SDIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

14
Freescale
H-2
Example
NEXT any CPU instruction
The address compared may be any address in the page zero memory and the only
restriction is that it should not be a register with flags cleared by reading the register.
The example shows the address compared to be port A data register and this should
not cause any problems in any applications.
High STOP Idd will be variable dependant upon the opcode following the STOP
instruction. The more bits set in the following opcode, the higher the STOP Idd. The
work around described above may be used on any 68HC05B32 or corrected version of
the 68HC705B32 without problem. It simply adds a 5 cycle delay to the recovery from
STOP and 3 bytes of additional code per STOP instruction but may alter the state of the
carry bit in the CCR.
Also for the D59J:
The EEPROM programming circuit only fully supports 16-byte simultaneous
programming mode and does not support single byte programming correctly.
The fault lies with the design of the EPROM array. A fault in the EPROM write data latch
circuitry causes a latch to be driven to logic 0 on both sides when the data bus for that
bit is logic 1. When the ELAT signal is removed, there is a race condition with the EPBS
signal which results in the data bus value being copied to all the EPROM latches.
Since 16-byte simultaneous programming functions correctly, it is a relatively simple
matter to emulate single byte programming by first initialising all 16 data latches to $00
and then writing the data to be written to the appropriate address.
This problem does not affect user application software in normally circumstances since
it only applies to programming the EPROM array. The serial programming software
should always simulate 16-byte programming. The Freescale software for
programming the 705B32 from an IBM compatible PC functions in 16 byte
programming mode. This program therefore correctly programs the EPROM.
In normal circumstances this errata does not affect the user application software. This
only affects software that programs the EPROM array. The parallel programming
bootloader software within the 705B32 ROM performs 16-byte programming and so
functions correctly.
STOP
BRSET 0,$00,NEXT
MC68HC705B32
MC68HC05B6
Rev. 4.1