XC68HC705B32CB Freescale Semiconductor, XC68HC705B32CB Datasheet - Page 289
XC68HC705B32CB
Manufacturer Part Number
XC68HC705B32CB
Description
IC MCU 2.1MHZ 32K OTP 56-DIP
Manufacturer
Freescale Semiconductor
Series
HC05r
Datasheet
1.MC68HC705B16CFN.pdf
(302 pages)
Specifications of XC68HC705B32CB
Core Processor
HC05
Core Size
8-Bit
Speed
2.1MHz
Connectivity
SCI
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Size
32KB (32K x 8)
Program Memory Type
OTP
Eeprom Size
256 x 8
Ram Size
528 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 8x8b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
56-SDIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Pull-down, pull-up These terms refer to resistors, sometimes internal to the device, which are
PWM
QFP
RAM
RFI
RTI
ROM
RS-232C
SAR
SCI
Set
Silicon glen
Single chip mode
SPI
Test mode
TTL
UART
VCO
Watchdog
Wired-OR
Word
XIRQ
MC68HC05B6
permanently connected to either ground or V
Pulse width modulation. This term is used to describe a technique where the
width of the high and low periods of a waveform is varied, usually to enable
a representation of an analog value.
Quad flat pack package.
Random access memory. Fast read and write, but contents are lost when the
power is removed.
Radio frequency interference.
Real-time interrupt.
Read-only memory. This type of memory is programmed during device
manufacture and cannot subsequently be altered.
A standard serial communications protocol.
Successive approximation register.
Serial communications interface.
‘1’ — the logic one state; the opposite of ‘clear’.
An area in the central belt of Scotland, so called because of the
concentration of semiconductor manufacturers and users found there.
In this mode the device functions as a self contained unit, requiring only I/O
devices to complete a system.
Serial peripheral interface.
This mode is intended for factory testing.
Transistor-transistor logic.
Universal asynchronous receiver transmitter.
Voltage controlled oscillator.
see ‘COP’.
A means of connecting outputs together such that the resulting composite
output state is the logical OR of the state of the individual outputs.
Two bytes; 16 bits.
Non-maskable interrupt request. The overline indicates that this has an
active-low signal format.
GLOSSARY
DD
.
Freescale
TPG
iii
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