M30803FGFP#D3 Renesas Electronics America, M30803FGFP#D3 Datasheet - Page 242
M30803FGFP#D3
Manufacturer Part Number
M30803FGFP#D3
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D3
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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M
R
R
e
E
1
v
J
6
Timing requirements (referenced to V
Table 28.6 External clock input
Table 28.7 Memory expansion and microprocessor modes
Note: Calculated according to the BCLK frequency as follows:
1 .
t
t
t
t
t
t
0
t
t
t
t
t
t
t
t
t
t
t
C
su(DB-BCLK)
su(RDY-BCLK )
su(HOLD-BCLK )
h(RD-DB)
h(CAS -DB)
h(BCLK -RDY)
h(BCLK-HOLD )
d(BCLK-HLDA )
t
t
t
t
t
ac1(RD-DB)
ac1(AD-DB)
ac2(RD-DB)
ac3(RD-DB)
ac4(RAS-DB)
ac4(CAS-DB)
ac4(CAD-DB)
ac2(AD-DB)
ac3(AD-DB)
9
Symbol
c
w(H)
w(L)
r
f
0 .
Symbol
8 /
B
0
0
0
1
Note that inserting wait or using lower operation frequency f(BCLK) is needed when
calculated value is negative.
A
G
8
u
7
t
t
t
t
t
t
t
t
t
o r
ac4(RAS – DB)
ac4(CAS – DB)
ac4(CAD – DB)
ac1(RD – DB)
ac1(AD – DB)
ac2(RD – DB)
ac2(AD – DB)
ac3(RD – DB)
ac3(AD – DB)
. g
0 -
u
1
0
p
0
External clock input cycle time
External clock input HIGH pulse width
External clock input LOW pulse width
External clock rise time
External clock fall time
, 2
0
2
0
Data input access time (RD standard, no wait)
Data input access time (AD standard, CS standard, no wait)
Data input access time (RD standard, with wait)
Data input access time (AD standard, CS standard, with wait)
Data input access time
Data input access time
multiplex bus area)
Data input access time (RAS standard, DRAM access)
Data input access time (CAS standard, DRAM access)
Data input access time (CAD standard, DRAM access)
Data input setup time
RDY input setup time
HOLD input setup time
Data input hold time
Data input hold time
RDY input hold time
HOLD input hold time
HLDA output delay time
0
5
=
=
=
=
=
=
=
=
=
Page 229
f
f
f
f
(BCLK)
(BCLK)
(BCLK)
(BCLK)
f
f
10 X m
10 X n
10 X m
10 X n
f
(BCLK)
f
(BCLK)
(BCLK)
(BCLK)
10 X m
10 X n
10 X l
f
10
10
(BCLK)
9
9
9
9
9
9
9
9
9
X 2
X 2
X 2
X 2
X 2
X 2
f o
– 35
– 35
– 35
– 35
– 35
– 35
3
– 35
– 35
– 35
2
9
Parameter
(RD standard, when accessing multiplex bus area)
(AD standard, CS standard, when accessing
[ns]
[ns] (m=3, 5 and 7 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (n=2, 3 and 4 when 1 wait, 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 2 wait and 3 wait, respectively)
[ns]
[ns] (n=5 and 7 when 2 wait and 3 wait, respectively)
[ns] (m=3 and 5 when 1 wait and 2 wait, respectively)
[ns] (n=1 and 3 when 1 wait and 2 wait, respectively)
[ns] (l=1 and 2 when 1 wait and 2 wait, respectively)
Parameter
CC
= 5V, V
SS
= 0V at Topr = 25
Min.
50
22
22
o
Standard
C unless otherwise specified)
28. Electrical characteristics
Min.
26
26
30
Standard
0
0
0
0
Max.
5
5
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
(Note)
Max.
25
Unit
ns
ns
ns
ns
ns
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
= 5V
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