M30803FGFP#D3 Renesas Electronics America, M30803FGFP#D3 Datasheet - Page 78
M30803FGFP#D3
Manufacturer Part Number
M30803FGFP#D3
Description
IC M16C MCU FLASH 256K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/80r
Datasheet
1.M30803FGGPU3.pdf
(360 pages)
Specifications of M30803FGFP#D3
Core Processor
M16C/80
Core Size
16-Bit
Speed
20MHz
Connectivity
SIO, UART/USART
Peripherals
DMA, PWM, WDT
Number Of I /o
85
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 10x10b, D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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1
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Table 9.4 Interrupt Priority Levels
6
1 .
Interrupt priority
0
C
level select bit
9
0 .
8 /
B
0
b2
0
0
0
1
1
1
1
0
9.10 Rewrite the interrupt control register
0
0
1
Table 9.4 shows how interrupt priority levels are set. Table 9.5 shows interrupt enable levels in
relation to the processor interrupt priority level (IPL).
The following lists the conditions under which an interrupt request is acknowledged:
• Interrupt enable flag (I flag)
• Interrupt request bit
• Interrupt priority level
The interrupt enable flag (I flag), interrupt request bit, interrupt priority level select bit, and the proces-
sor interrupt priority level (IPL) all are independent of each other, so they do not affect any other bit.
When a instruction to rewrite the interrupt control register is executed but the interrupt is disabled, the
interrupt request bit is not set sometimes even if the interrupt request for that register has been gener-
ated. This will depend on the instruction. If this creates problems, use the below instructions to change
the register.
Instructions : AND, OR, BCLR, BSET
A
G
8
u
7
1
b1
0
0
1
0
0
1
1
o r
. g
0 -
u
1
0
p
0
, 2
0
0
1
1
0
1
0
1
b0
0
2
0
0
Level 0 (interrupt disabled)
5
Level 1
Level 2
Level 3
Level 4
Level 5
Level 6
Level 7
Interrupt priority level
Page 65
f o
3
2
9
= 1
= 1
> Processor interrupt priority level (IPL)
Priority
order
High
Low
Table 9.5 IPL and Interrupt Enable Levels
Processor interrupt
priority level (IPL)
IPL
0
0
0
0
1
1
1
1
2
IPL
0
0
1
1
0
0
1
1
1
IPL
0
1
0
1
0
1
1
0
0
Interrupt levels 5 and above are enabled.
Interrupt levels 1 and above are enabled.
Interrupt levels 2 and above are enabled.
Interrupt levels 3 and above are enabled.
Interrupt levels 4 and above are enabled.
Interrupt levels 6 and above are enabled.
Interrupt levels 7 and above are enabled.
All maskable interrupts are disabled.
Enabled interrupt priority
9. Interrupt Outline
levels
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