MC9S12UF32PB Freescale Semiconductor, MC9S12UF32PB Datasheet - Page 85

• Manufacturer Part Number: MC9S12UF32PB
• Description: IC MCU 32K FLASH 30MHZ 64LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS12r

Specifications of MC9S12UF32PB

• Core Processor: HCS12
• Core Size: 16-Bit
• Speed: 30MHz
• Connectivity: ATA, Compact Flash, EBI/EMI, Memory Stick, MMC, SCI, SD, Smart Media, USB
• Peripherals: POR, WDT
• Number Of I /o: 41
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 3.5K x 8
• Voltage - Supply (vcc/vdd): 2.25 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Data Converters: -

Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the HCS12 Core User Guide for information on resets and
interrupts. Both local masking and CCR masking are included as listed in Table 5-1. System resets can
be generated through external control of the RESET pin, through the clock and reset generator module
CRG_U. Refer to the CRG_U User Guide for detailed information on reset generation.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Freescale Semiconductor
Vector Address
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
$FFF6, $FFF7
$FFF4, $FFF5
$FFF2, $FFF3
$FFF0, $FFF1
$FFEE, $FFEF
$FFEC, $FFED
$FFEA, $FFEB
$FFE8, $FFE9
$FFE6, $FFE7
$FFE4, $FFE5
$FFE2, $FFE3
$FFE0, $FFE1
$FFDE, $FFDF
$FFDC, $FFDD
$FFDA, $FFDB
$FFD8, $FFD9
$FFD6, $FFD7
$FFD4, $FFD5
$FFD2, $FFD3
$FFD0, $FFD1
$FFCE, $FFCF
USB set endpoint configuration register
Unimplemented instruction trap
Pulse accumulator A overflow
Pulse accumulator input edge
USB Setup command related
Interrupt Source
Real Time Interrupt
USB status change
USB Endpoint 0 IN
COP failure reset
Timer channel 0
Timer channel 1
Timer channel 2
Timer channel 3
Timer channel 4
Timer channel 5
Timer channel 6
Timer channel 7
Timer overflow
Table 5-1 Interrupt Vector Locations
Reserved
Reserved
request
Reset
XIRQ
SWI
IRQ
SCI
System on a Chip Guide — 9S12UF32DGV1/D V01.05
Mask
CCR
None
None
None
None
None
X-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
I-Bit
-
UIMR (SETOVRIE, SETUP)
UIMR(USSCIE, URSCIE)
(TIE, TCIE, RIE, ILIE)
UCCSR(SETECRIE)
UEPCSR0 (TCIE)
INTCR (IRQEN)
COP rate select
CRGINT (RTIE)
Local Enable
PACTL (PAOVI)
TSCR2 (TOI)
PACTL (PAI)
Reserved
Reserved
TIE (C0I)
TIE (C1I)
TIE (C2I)
TIE (C3I)
TIE (C4I)
TIE (C5I)
TIE (C6I)
TIE (C7I)
SCICR2
None
None
None
None
HPRIO Value
to Elevate
$EC
$DE
$DC
$DA
$CE
$EE
$EA
$E8
$E6
$E4
$E2
$E0
$D8
$D6
$D4
$D2
$D0
$F2
$F0
–
–
–
–
–
–
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