M30260F6AGP#U3 Renesas Electronics America, M30260F6AGP#U3 Datasheet - Page 196
![IC M16C MCU FLASH 48K 48LQFP](/photos/28/61/286102/48-lqfp__plqp0048kb-a_sml.jpg)
M30260F6AGP#U3
Manufacturer Part Number
M30260F6AGP#U3
Description
IC M16C MCU FLASH 48K 48LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/Tiny/26r
Specifications of M30260F6AGP#U3
Core Processor
M16C/60
Core Size
16-Bit
Speed
20MHz
Connectivity
I²C, IEBus, SIO, UART/USART
Peripherals
DMA, PWM, Voltage Detect, WDT
Number Of I /o
39
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30260F6AGP#U3M30260F6AGP#D3
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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1
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Figure 13.1.6.1. Transmit and Receive Timing in SIM Mode
6
0
2
9
C
0 .
B
2 /
0
0
2
6
0
A
(1) Transmit Timing
F
Transfer Clock
TE bit in U2C1
register
TxD
RxD
TXEPT bit in U2
C0 register
IR bit in S2TIC
register
Transfer Clock
RE bit in U2C1
register
Transmit Waveform
from the
Transmitting End
TxD2
RxD
RI bit in U2C1
register
IR bit in S2RIC
register
TI bit in U2C1
register
Parity Error Signal
returned from
Receiving End
NOTES:
2
(2) Receive Timing
e
The above timing diagram applies to the case where data is
transferred in the direct format.
The above timing diagram applies to the case where data is
transferred in the direct format.
0 -
G
b
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
• U2MR register STPS bit = 0 (1 stop bit)
• U2MR register PRY bit = 1 (even)
• U2C0 register UFORM bit = 0 (LSB first)
• U2C1 register U2LCH bit = 0 (no reverse)
• U2C1 register U2IRSCH bit = 1 (transmit is completed)
2
2
2
1. Because TxD
2. Because TxD
1 .
pin Level
pin Level
2
o r
0
signal sent back from receiver.
and the parity error signal received.
, 5
u
0
p
2
0
(
(1)
(2)
M
0
7
1
6
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"0"
"1"
"1"
"0"
"1
"0
"0
"
"
"
C
page 177
2
2
2 /
and RxD
and RxD
6
, A
Start
ST
ST
ST
M
Start
ST
2
2
bit
bit
are connected, this is composite waveform consisting of the TxD
are connected, this is composite waveform consisting of the transmitter's transmit waveform
1
f o
D
D
D
D
6
0
0
0
0
3
C
D
D
D
D
2
1
1
1
2 /
1
9
TC
Tc
D
D
D
D
6
2
2
2
2
, B
D
D
D
D
3
3
3
3
M
D
D
D
D
4
4
4
4
1
D
D
D
D
6
5
5
5
5
C
D
D
D
D
2 /
Data is written to
the UARTi register
6
6
6
6
6
D
D
D
D
7
7
7
7
) T
Parity
Parity
bit
P
P
bit
P
P
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
Tc = 16 (n + 1) / fi or 16 (n + 1) / f
SP
SP
SP
SP
Stop
Stop
bit
fi : frequency of U2BRG count source (f
f
n : value set to U2BRG
fi : frequency of U2BRG count source (f
f
n : value set to U2BRG
bit
EXT
EXT
Set to "0" by an interrupt request acknowledgement or by program
Set to "0" by an interrupt request acknowledgement or by program
: frequency of U2BRG count source (external clock)
: frequency of U2BRG count source (external clock)
ST
ST
ST
ST
An interrupt routine
detects "H" or "L"
Data is transferred from the U2TB
register to the UART2 transmit
register
An "L" signal is applied from the SIM
card due to a parity error
D
D
D
D
0
0
0
0
Read the U2RB register
D
D
D
D
1
1
1
1
D
D
D
D
2
2
2
2
EXT
EXT
D
TxD
to a parity error
D
D
D
3
3
3
3
2
2
D
D
D
D
outputs "L" due
4
4
4
output and the parity error
4
An interrupt routine detects
"H" or "L"
D
D
D
D
5
5
5
5
1SIO
1SIO
D
D
D
D
6
6
6
6
, f
, f
D
D
D
D
2SIO
2SIO
7
7
7
7
P
P
P
P
, f
, f
8SIO
8SIO
SP
SP
SP
SP
, f
, f
32SIO
32SIO
)
)
13. Serial I/O
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