M30280F6HP#D3 Renesas Electronics America, M30280F6HP#D3 Datasheet - Page 173

• Manufacturer Part Number: M30280F6HP#D3
• Description: MCU 3/5V 48K I-TEMP 80-LQFP
• Manufacturer: Renesas Electronics America
• Series: M16C™ M16C/Tiny/28r

Specifications of M30280F6HP#D3

• Core Processor: M16C/60
• Core Size: 16-Bit
• Speed: 20MHz
• Connectivity: I²C, IEBus, SIO, UART/USART
• Peripherals: DMA, POR, PWM, Voltage Detect, WDT
• Number Of I /o: 71
• Program Memory Size: 48KB (48K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -

M
R
R
13.2 Interrupt Operation
13.3 DMA Support
1
e
E
Table 13.4 Interrupt Assignment
. v
6
J
Figure 13.18 IC/OC Interrupt and DMA request generation
The IC/OC interrupt contains several request causes. Figure 13.18 shows the IC/OC interrupt block dia-
gram and Table 13.4 shows the IC/OC interrupt assignation.
When either the base timer reset request or base timer overflow request is generated, the IR bit in the BTIC
register corresponding to the IC/OC base timer interrupt is set to "1" (with an interrupt request). Also when
an interrupt request in each eight channels (channel i) is generated, the bit i in the G1IR register is set to "1"
(with an interrupt request). At this time, if the bit i in the G1IE0 register is "1" (IC/OC interrupt 0 request
enabled), the IR bit in the ICOC0IC register corresponding to the IC/OC interrupt 0 is set to "1" (with an
interrupt request). And if the bit i in the G1IE1 register is "1" (IC/OC interrupt 1 request enabled), the IR bit
in the ICOC1IC register corresponding to the IC/OC interrupt 1 is set to "1"(with an interrupt request).
Additionally, because each bit in the G1IR register is not automatically set to "0" even if the interrupt is
acknowledged, set to "0" by program. If these bits are left as "1", all IC/OC channel interrupt causes, which
are generated after setting the IR bit to "1", will be disabled.
IC/OC base timer interrupt
IC/OC interrupt 0
IC/OC interrupt 1
Each of the interrupt sources - the eight IC/OC channel interrupts and the one Base Timer interrupt - are
capable of generating a DMA request.
C
0
2
9
2 /
0 .
B
Channel 0 to 7 Interrupt requests
8
0
0
Interrupt
All register are read / write
0
G
4
J
Interrupt Select Logic
7
a
o r
Base timer overflow request
Base timer reset request
0 -
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u
2
p
3
0
, 1
0
(
M
2
1
0
0
6
7
C
2 /
page 151
, 8
M
ENABLE
1
G1IE0
6
C
Interrupt control register
2 /
f o
8
ICOC0IC(0045
ICOC0IC(0046
3
) B
8
BTIC(0047
5
REQUEST
16
)
16
16
G1IR
)
)
Base Timer Interrupt / DMA Request
ENABLE
G1IE1
DMA Requests (channel 0 to 7)
IC/OC base timer interrupt request
IC/OC interrupt 1 request
IC/OC interrupt 0 request
13. Timer S