MCHC908GR8VFAE Freescale Semiconductor, MCHC908GR8VFAE Datasheet - Page 74

• Manufacturer Part Number: MCHC908GR8VFAE
• Description: IC MCU 8K FLASH 8MHZ 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MCHC908GR8VFAE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SCI, SPI
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 7.5KB (7.5K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 6x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Resets and Interrupts
4.4.2.9 KBD0–KBD4 Pins
4.4.2.10 ADC (Analog-to-Digital Converter)
4.4.2.11 TBM (Timebase Module)
Technical Data
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A logic 0 on a keyboard interrupt pin latches an external interrupt
request.
When the AIEN bit is set, the ADC module is capable of generating a
CPU interrupt after each ADC conversion. The COCO/IDMAS bit is not
used as a conversion complete flag when interrupts are enabled.
The timebase module can interrupt the CPU on a regular basis with a
rate defined by TBR2–TBR0. When the timebase counter chain rolls
over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase
interrupt, the counter chain overflow will generate a CPU interrupt
request.
Interrupts must be acknowledged by writing a logic 1 to the TACK bit.
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Noise flag (NF) — NF is set when the SCI detects noise on
incoming data or break characters, including start, data, and stop
bits. The noise error interrupt enable bit, NEIE, enables NF to
generate SCI error CPU interrupt requests. NF is in SCI status
register 1. NEIE is in SCI control register 3.
Framing error bit (FE) — FE is set when a logic 0 occurs where the
receiver expects a stop bit. The framing error interrupt enable bit,
FEIE, enables FE to generate SCI error CPU interrupt requests.
FE is in SCI status register 1. FEIE is in SCI control register 3.
Parity error bit (PE) — PE is set when the SCI detects a parity error
in incoming data. The parity error interrupt enable bit, PEIE,
enables PE to generate SCI error CPU interrupt requests. PE is in
SCI status register 1. PEIE is in SCI control register 3.
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Resets and Interrupts
MC68HC908GR8 — Rev 4.0
MOTOROLA