R5F21237KFP#U0 Renesas Electronics America, R5F21237KFP#U0 Datasheet - Page 348
R5F21237KFP#U0
Manufacturer Part Number
R5F21237KFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21237KFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
16MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21237KFP#U0R5F21237KFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 16.25
IIC Bus Control Register 2
b7 b6 b5 b4
NOTES:
1.
2.
3.
4.
When w riting to the SDAO bit, w rite 0 to the SDAOP bit using the MOV instruction simultaneously.
Do not w rite during transfer operation.
This bit is enabled in master mode. When w rite to the BBSY bit, w rite 0 to the SCP bit using the MOV instruction
simultaneously. Execute the same w ay w hen the start condition is regenerating.
This bit is disabled w hen the clock synchronous serial format is used.
b3 b2 b1
ICCR2 Register
b0
Bit Symbol
SDAOP
Symbol
IICRST
SDAO
ICCR2
SCLO
BBSY
Page 326 of 501
(b0)
(b2)
SCP
—
—
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
IIC control part reset bit
Nothing is assigned. If necessary, set to 0.
When read, the content is 1.
SCL monitor flag
SDAO w rite protect bit
SDA output value control
bit
Start / stop condition
generation disable bit
Bus busy bit
Address
Bit Name
00B9h
(4)
When hang-up occurs due to communication failure
during I
control part of I
and initializing register.
1 : SCL pin is set to “H”
When read, its content is 1.
When read
0 : SDA pin output is held “L”
1 : SDA pin output is held “H”
When w rite
0 : SDA pin output is changed to “L”
1 : SDA pin output is changed to high-impedance
When w rite to BBSY bit, w rite 0 simultaneously.
When read, its content is 1.
Writing 1 is disabled.
When read
0 : Bus is in released state
1 : Bus is in occupied state
When w rite
0 : Generates stop condition
1 : Generates start condition
0 : SCL pin is set to “L”
When rew rite to SDAO bit, w rite 0 simultaneously.
(SDA signal changes from “H” to “L” w hile SCL
(“H” output is external pull-up resistor)
(SDA signal changes from “L” to “H” w hile SCL
signal is in “H” state)
signal is in “H” state)
2
C bus interface operation and w rite 1, reset
(1,2)
(3)
2
C bus interface w ithout setting port
16. Clock Synchronous Serial Interface
After Reset
01111101b
Function
(3)
(1)
RW
RW
RW
RW
RW
RW
RO
—
—
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