R5F21237KFP#U0 Renesas Electronics America, R5F21237KFP#U0 Datasheet - Page 381
R5F21237KFP#U0
Manufacturer Part Number
R5F21237KFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21237KFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
16MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21237KFP#U0R5F21237KFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
17.4
Figure 17.4
17.4.1
IR bit in the TRAIC
SBDCT flag in the
Figure 17.4 shows a Typical Operation when Sending a Header Field. Figure 17.5 and Figure 17.6 show an
Example of Header Field Transmission Flowchart.
When transmitting a header field, the hardware LIN operates as described below.
LINST register
Functional Description
(1) When the TSTART bit in the TRACR register for timer RA is set by writing 1 in a program, the
(2) When timer RA underflows upon reaching the terminal count, the hardware LIN reverses the output of
(3) The hardware LIN transmits 55h via UART0.
(4) The hardware LIN transmits an ID field via UART0 after it finished sending 55h.
(5) The hardware LIN performs communication for a response field after it finished sending the ID field.
TXD0 pin
Master Mode
• When LINE bit = 1 (Causes LIN to start operating), MST bit = 1 (Master mode), SBIE bit = 1
hardware LIN outputs a low-level signal from the TXD0 pin for the period that is set in the TRAPRE
and TRA registers for timer RA.
the TXD0 pin and sets the SBDCT flag in the LINST register to 1. Furthermore, if the SBIE bit in the
LINCR register is set to 1, it generates a timer RA interrupt.
register
(Enables Synch Break detection interrupt)
Typical Operation when Sending a Header Field
1
0
1
0
1
0
Page 359 of 501
(1)
Synch Break
(2)
(3)
Set by writing 1 to the
B1CLR bit in the LINST
register
Cleared to 0 upon
acceptance of interrupt
request or by a program
Synch Field
(4)
IDENTIFIER
17. Hardware LIN
(5)
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