R5F21237KFP#U0 Renesas Electronics America, R5F21237KFP#U0 Datasheet - Page 414
R5F21237KFP#U0
Manufacturer Part Number
R5F21237KFP#U0
Description
IC R8C/23 MCU FLASH 48LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/23r
Datasheet
1.R5F21237DFPU0.pdf
(551 pages)
Specifications of R5F21237KFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
16MHz
Connectivity
CAN, I²C, LIN, SIO, SSU, UART/USART
Peripherals
POR, Voltage Detect, WDT
Number Of I /o
41
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2.5K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-LQFP
For Use With
RCDK8C - KIT DEV EVAL FOR CAN R8C/23R0E521237CPE00 - EMULATOR COMPACT R8C/20/21/22/23
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21237KFP#U0R5F21237KFP#U1
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/22 Group, R8C/23 Group
Rev.2.00 Aug 20, 2008
REJ09B0251-0200
Figure 18.24
18.12.1 Reception
CANbus
RecReq bit
InvalData bit
NewData bit
MsgLost bit
CAN0 successful
reception
interrupt
RecState bit
RecSucc bit
MBOX bit
(1) If a SOF is detected on the CAN bus, the RecState bit in the C0STR register is set to 1 (During reception)
(2) The message successfully is received and the NewData bit in the C0MCTLi register of the reception slot is
(3) If the interrupt enable bit in the C0ICR register of the slot is set to 1 (interrupt enabled), the CAN0
(4) Set the NewData bit to 0 (the content of the slot is read out or still under processing by the CPU) by a
(5) When next CAN message is received before the NewData bit is set to 0 by a program or a receive request to
Figure 18.24 shows the Timing of Receive Data Frame Sequence. This is an operation example when
consecutive messages are received.
immediately and the slot starts receiving a message.
set to 1 (stored new data in slot). The InvalData bit in the C0MCTLi register is set to 1 (the message is
being updated) at the same time and set to 0 (the message is valid) after the message completely is stored to
the slot.
successful reception interrupt request is generated and the MBOX and RecSucc bits in the C0STR register
change.
program and read the message from the slot.
a slot is canceled, the MsgLost bit in the C0MCTLj register is set to 1 (this slot already contained a
message) and new message is stored in a slot. CAN0 successful reception interrupt and the C0STR register
change the same as (3).
i = 0 to 15
Timing of Receive Data Frame Sequence
SOF
(1)
Page 392 of 501
ACK
EOF
(2)
(2)
(3)
IFS
SOF
Receive slot No.
(4)
ACK
EOF
(5)
(5)
(5)
18. CAN Module
IFS
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