AD8557ARZ Analog Devices Inc, AD8557ARZ Datasheet - Page 14

• Manufacturer Part Number: AD8557ARZ
• Description: IC AMP CHOPPER 2MHZ 55MA 8SOIC
• Manufacturer: Analog Devices Inc
• Series: DigiTrim®r

Specifications of AD8557ARZ

• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 18nA
• Voltage - Input Offset: 2µV
• Current - Supply: 1.8mA
• Current - Output / Channel: 55mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Input Offset Voltage: 12µV
• Gain Db Min: 28dB
• Bandwidth: 2MHz
• Amplifier Output: Single Ended / Differential
• Cmrr: 112dB
• Supply Voltage Range: 2.7V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Slew Rate: -

THEORY OF OPERATION
A1, A2, R1, R2, R3, P1, and P2 form the first gain stage of the
differential amplifier. A1 and A2 are auto-zeroed op amps that
minimize input offset errors. P1 and P2 are digital potentiome-
ters, guaranteed to be monotonic. Programming P1 and P2
allows the first stage gain to be varied from 2.8 to 5.2 with 7-bit
resolution (see Table 6 and Equation 1), giving a fine gain
adjustment resolution of 0.49%. Because R1, R2, R3, P1, and P2
each have a similar temperature coefficient, the first stage gain
temperature coefficient is lower than 100 ppm/°C.
A3, R4, R5, R6, R7, P3, and P4 form the second gain stage of the
differential amplifier. A3 is an auto-zeroed op amp that mini-
mizes input offset errors and also includes an output buffer. P3
and P4 are digital potentiometers, which allow the second stage
gain to be varied from 10 to 250 in eight steps (see Table 7). R4,
R5, R6, R7, P3, and P4 each have a similar temperature coefficient,
so the second stage gain temperature coefficient is lower than
100 ppm/°C. The output stage of A3 is supplied from a buffered
version of VCLAMP instead of VDD, allowing the positive
swing to be limited.
A4 implements a voltage buffer, which provides the positive
supply to the output stage of A3. Its function is to limit VOUT
to a maximum value, useful for driving analog-to-digital
converters (ADC) operating on supply voltages lower than
VDD. The input to A4, VCLAMP, has a very high input
resistance. It should be connected to a known voltage and not
be left floating. However, the high input impedance allows the
clamp voltage to be set using a high impedance source, such as a
potential divider. If the maximum value of VOUT does not
need to be limited, VCLAMP should be connected to VDD.
An 8-bit digital-to-analog converter (DAC) is used to generate a
variable offset for the amplifier output. This DAC is guaranteed
AD8557
GAIN1
≈
2
.
8
×
⎛
⎜
⎝
5.2
2.8
⎞
⎟
⎠
⎛
⎜
⎝
Code
1
27
⎞
⎟
⎠
Rev. B | Page 14 of 24
(1)
to be monotonic. To preserve the ratiometric nature of the input
signal, the DAC references are driven from VSS and VDD, and
the DAC output can swing from VSS (Code 0) to VDD (Code
255). The 8-bit resolution is equivalent to 0.39% of the difference
between VDD and VSS, for example, 19.5 mV with a 5 V supply.
The DAC output voltage (VDAC) is given approximately by
where the temperature coefficient of VDAC is lower than
200 ppm/°C.
The amplifier output voltage (VOUT) is given by
where GAIN is the product of the first and second stage gains.
VDAC
VOUT
VNEG
VPOS
≈
=
⎛
⎜
⎝
GAIN
VDD
A1
VDD
A2
VSS
VSS
Code
Figure 45. Functional Schematic
256
(
+
VPOS
DIGIN
R1
R3
R2
VDD
VSS
0
P1
P2
5 .
R4
R5
⎞
⎟
⎠
(
−
VDD
P4
VNEG
P3
−
A3
VDD
VSS
R6
R7
VSS
)
+
VDAC
)
VCLAMP
+
VSS
A4
VDD
VSS
VOUT
(2)
(3)