AD8557ARZ Analog Devices Inc, AD8557ARZ Datasheet - Page 16

• Manufacturer Part Number: AD8557ARZ
• Description: IC AMP CHOPPER 2MHZ 55MA 8SOIC
• Manufacturer: Analog Devices Inc
• Series: DigiTrim®r

Specifications of AD8557ARZ

• Amplifier Type: Chopper (Zero-Drift)
• Number Of Circuits: 1
• Gain Bandwidth Product: 2MHz
• Current - Input Bias: 18nA
• Voltage - Input Offset: 2µV
• Current - Supply: 1.8mA
• Current - Output / Channel: 55mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Input Offset Voltage: 12µV
• Gain Db Min: 28dB
• Bandwidth: 2MHz
• Amplifier Output: Single Ended / Differential
• Cmrr: 112dB
• Supply Voltage Range: 2.7V To 5.5V
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Output Type: -
• -3db Bandwidth: -
• Slew Rate: -

OPEN WIRE FAULT DETECTION
The inputs to A1 and A2, VNEG and VPOS, each have a com-
parator to detect whether VNEG or VPOS exceeds a threshold
voltage, nominally VDD − 2.0 V. If VNEG > (VDD − 2.0 V) or
VPOS > (VDD − 2.0 V), VOUT is clamped to VSS. The output
current limit circuit is disabled in this mode, but the maximum
sink current is approximately 10 mA when VDD = 5 V. The
inputs to A1 and A2, VNEG and VPOS, are also pulled up to
VDD by currents IP1 and IP2. These are both nominally 16 nA
and matched to within 3 nA. If the inputs to A1 or A2 are
accidentally left floating, as with an open wire fault, IP1 and IP2
pull them to VDD, which would cause VOUT to swing to VSS,
allowing this fault to be detected. It is not possible to disable IP1
and IP2, nor the clamping of VOUT to VSS, when VNEG or
VPOS approaches VDD.
SHORTED WIRE FAULT DETECTION
The AD8557 provides fault detection in the case where VPOS,
VNEG, or VCLAMP shorts to VDD and VSS. Figure 46 shows
the voltage regions at VPOS, VNEG, and VCLAMP that trigger
an error condition. When an error condition occurs, the VOUT
pin is shorted to VSS. Table 8 lists the voltage levels shown in
Figure 46.
Table 8. Typical VINL, VINH, and VCLL Values
(VDD = 5 V)
Voltage
VINH
VINL
VCLL
AD8557
NORMAL
ERROR
ERROR
VPOS
WAVEFORM
Figure 46. Voltage Regions at VPOS, VNEG, and VCLAMP
Min (V)
3.9
0.195
1.0
CODE
VDD
VINH
VINL
VSS
that Trigger a Fault Condition
t
W0
0
Max (V)
4.2
0.55
1.2
t
WS
NORMAL
ERROR
ERROR
VNEG
VOUT Condition
Short to VSS fault detection
Short to VSS fault detection
Short to VSS fault detection
VDD
VINH
VINL
VSS
t
W1
1
VCLAMP
NORMAL
ERROR
Figure 47. Timing Diagram for Code 010011
t
WS
t
VDD
VCLL
VSS
W0
0
Rev. B | Page 16 of 24
t
WS
t
W0
0
t
WS
FLOATING VPOS, VNEG, OR VCLAMP FAULT
DETECTION
A floating fault condition at the VPOS, VNEG, or VCLAMP
pins is detected by using a low current to pull a floating input
into an error voltage range, defined in the previous section. In
this way, the VOUT pin is shorted to VSS when a floating input
is detected. Table 9 lists the currents used.
Table 9. Floating Fault Detection at VPOS, VNEG,
and VCLAMP
Pin
VPOS
VNEG
VCLAMP
DEVICE PROGRAMMING
Digital Interface
The digital interface allows the first stage gain, second stage
gain, and output offset to be adjusted and allows desired values
for these parameters to be permanently stored by selectively
blowing polysilicon fuses. To minimize pin count and board
space, a single-wire digital interface is used. The digital input
pin, DIGIN, has hysteresis to minimize the possibility of
inadvertent triggering with slow signals. It also has a pull-down
current sink to allow it to be left floating when programming is
not being performed. The pull-down ensures inactive status of
the digital input by forcing a dc low voltage on DIGIN.
A short pulse at DIGIN from low to high and back to low again,
such as between 50 ns and 10 μs long, loads a 0 into a shift
register. A long pulse at DIGIN, such as 50 μs or longer, loads a
1 into the shift register. The time between pulses should be at
least 10 μs. Assuming VSS = 0 V, voltages at DIGIN between
VSS and 0.2 × VDD are recognized as a low, and voltages at
DIGIN between 0.8 × VDD and VDD are recognized as a high.
A timing diagram example, Figure 47, shows the waveform for
entering Code 010011 into the shift register.
t
W1
1
Typical Current
16 nA pull-up
16 nA pull-up
0.2 μA pull-down
t
WS
t
W1
1
Goal of Current
Pull VPOS above VINH
Pull VNEG above VINH
Pull VCLAMP below VCLL