LMV712LD/NOPB National Semiconductor, LMV712LD/NOPB Datasheet - Page 10

• Manufacturer Part Number: LMV712LD/NOPB
• Description: IC OP AMP DUAL RR I/O W/SD 10LLP
• Manufacturer: National Semiconductor

Specifications of LMV712LD/NOPB

• Amplifier Type: General Purpose
• Number Of Circuits: 2
• Output Type: Rail-to-Rail
• Slew Rate: 5 V/µs
• Gain Bandwidth Product: 5MHz
• Current - Input Bias: 5.5pA
• Voltage - Input Offset: 400µV
• Current - Supply: 1.17mA
• Current - Output / Channel: 50mA
• Voltage - Supply, Single/dual (±): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 10-LLP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• -3db Bandwidth: -
• Lead Free Status / Rohs Status: Details
• Other names: LMV712LD; LMV712LDTR

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Application Information
THEORY OF OPERATION
The LMV712 dual op amp is derived from the LMV711 single
op amp.
nel of the LMV712.
Rail-to-Rail input is achieved by using in parallel, one NMOS
differential pair (MN1 and MN2) and one PMOS differential
pair (MP1 and MP2). When the common mode input voltage
(V
off. When V
pair is on. When V
cides how much current each differential pair will get. This
special logic ensures stable and low distortion amplifier op-
eration within the entire common mode voltage range.
Because both input stages have their own offset voltage
(V
comes a function of V
above V
formance Characteristics section. Caution should be taken in
situations where input signal amplitude is comparable to
V
situations, it is necessary for the input signal to avoid the
crossover point.
The current coming out of the input differential pairs gets mir-
rored through two folded cascode stages (Q1, Q2, Q3, Q4)
into the "class AB control" block. This circuitry generates volt-
age gain, defines the op amp's dominant pole and limits the
maximum current flowing at the output stage. MN3 introduces
a voltage level shift and acts as a high impedance to low
impedance buffer.
The output stage is composed of a PMOS and a NPN tran-
sistor in a common source/emitter configuration, delivering a
rail-to-rail output excursion.
The MN4 transistor ensures that the LMV712 output remains
near V
OS
CM
OS
value and/or the design requires high accuracy. In these
) characteristic, the offset voltage of the LMV712 be-
) is near V
−
−
when the amplifier is in shutdown mode.
Figure 1
. Refer to the "V
CM
is near V
+
, the NMOS pair is on and the PMOS pair is
contains a simplified schematic of one chan-
CM
is between V
CM
−
, the NMOS pair is off and the PMOS
. V
OS
OS
vs. V
has a crossover point at 1.4V
CM
+
" curve in the Typical Per-
and V
−
, internal logic de-
FIGURE 1.
10
SHUTDOWN PIN
The LMV712 offers independent shutdown pins for the dual
amplifiers. When the shutdown pin is tied low, the respective
amplifier shuts down and the supply current is reduced to less
than 1µA. In shutdown mode, the amplifier's output level stays
at V
2.7V is applied to the shutdown pin, the amplifier is enabled.
As the amplifier is coming out of the shutdown mode, the out-
put waveform ramps up without any glitch. This is demon-
strated in
−
. In a 2.7V operation, when a voltage between 1.5V to
Figure
2.
FIGURE 2.
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