AD8021AR Analog Devices Inc, AD8021AR Datasheet - Page 20

• Manufacturer Part Number: AD8021AR
• Description: IC OPAMP VF LN LP LDIST 8SOIC
• Manufacturer: Analog Devices Inc

Specifications of AD8021AR

• Slew Rate: 460 V/µs
• Rohs Status: RoHS non-compliant
• Design Resources: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
• Amplifier Type: Voltage Feedback
• Number Of Circuits: 1
• -3db Bandwidth: 560MHz
• Current - Input Bias: 7.5µA
• Voltage - Input Offset: 400µV
• Current - Supply: 7.8mA
• Current - Output / Channel: 70mA
• Voltage - Supply, Single/dual (±): 4.5 V ~ 24 V, ±2.25 V ~ 12 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• No. Of Amplifiers: 1
• Bandwidth: 560MHz
• No. Of Pins: 8
• Operating Temperature Range: -40°C To +85°C
• Peak Reflow Compatible (260 C): No
• Input Bias Current: 7500nA
• Output Type: -
• Gain Bandwidth Product: -
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

AD8021
C
Table 6. Recommended Component Values
Noise Gain
(Noninverting
Gain)
1
2
5
10
20
100
With the AD8021, a variety of trade-offs can be made to fine-
tune its dynamic performance. Sometimes more bandwidth
or slew rate is needed at a particular gain. Reducing the
compensation capacitance, as illustrated in Figure 7, increases
the bandwidth and peaking due to a decrease in phase margin.
On the other hand, if more stability is needed, increasing the
compensation capacitor decreases the bandwidth while
increasing the phase margin.
As with all high speed amplifiers, parasitic capacitance and
inductance around the amplifier can affect its dynamic
response. Often, the input capacitance (due to the op amp itself,
as well as the PC board) has a significant effect. The feedback
resistance, together with the input capacitance, can contribute
to a loss of phase margin, thereby affecting the high frequency
response, as shown in Figure 14. A capacitor (C
with the feedback resistor can compensate for this phase loss.
F
= C
L
= 0, R
L
= 1 kΩ, R
R
75
49.9
49.9
49.9
49.9
49.9
S
(Ω)
IN
= 49.9 Ω (see Figure 49).
R
75
499
1 k
1 k
1 k
1 k
F
(Ω)
R
NA
499
249
110
52.3
10
G
(Ω)
C
10
7
2
0
0
0
F
) in parallel
COMP
(pF)
Rev. F | Page 20 of 28
Slew Rate (V/μs)
120
150
300
420
200
34
Additionally, any resistance in series with the source creates a
pole with the input capacitance (as well as dampen high
frequency resonance due to package and board inductance
and capacitance), the effect of which is shown in Figure 15.
It must also be noted that increasing resistor values increases
the overall noise of the amplifier and that reducing the feedback
resistor value increases the load on the output stage, thus
increasing distortion (see Figure 22).
USING THE DISABLE FEATURE
When Pin 8 ( DISABLE ) is higher than Pin 1 (LOGIC
REFERENCE) by approximately 2 V or more, the part is
enabled. When Pin 8 is brought down to within about 1.5 V
of Pin 1, the part is disabled. See Table 1 for exact disable and
enable voltage levels. If the disable feature is not used, Pin 8 can
be tied to V
ground or logic low. Alternatively, if Pin 1 and Pin 8 are not
connected, the part is in an enabled state.
−3 dB
SS BW
(MHz)
490
205
185
150
42
6
S
or a logic high source, and Pin 1 can be tied to
Output Noise
(AD8021 Only)
(nV/√Hz)
2.1
4.3
10.7
21.2
42.2
211.1
Output Noise
(AD8021 with Resistors)
(nV/√Hz)
2.8
8.2
15.5
27.9
52.7
264.1