TSH72CDT STMicroelectronics, TSH72CDT Datasheet - Page 21

IC OP AMP DUAL LP WIDE 8-SOIC

TSH72CDT

Manufacturer Part Number
TSH72CDT
Description
IC OP AMP DUAL LP WIDE 8-SOIC
Manufacturer
STMicroelectronics
Datasheet

Specifications of TSH72CDT

Amplifier Type
General Purpose
Number Of Circuits
2
Output Type
Rail-to-Rail
Slew Rate
118 V/µs
Gain Bandwidth Product
65MHz
-3db Bandwidth
100MHz
Current - Input Bias
6µA
Voltage - Input Offset
800µV
Current - Supply
9.8mA
Current - Output / Channel
55mA
Voltage - Supply, Single/dual (±)
3 V ~ 12 V, ±1.5 V ~ 6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
8-SOIC
Number Of Channels
2
Voltage Gain Db
84 dB
Common Mode Rejection Ratio (min)
72 dB
Input Offset Voltage
10 mV
Operating Supply Voltage
5 V, 9 V
Supply Current
21 mA
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Maximum Dual Supply Voltage
+/- 6 V
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Manufacturer
Quantity
Price
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Quantity:
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TSH70,71,72,73,74,75
5
5.1
5.2
Testing Conditions
Layout precautions
To use the TSH7X circuits in the best manner at high frequencies, some precautions have to
be taken for power supplies:
Maximum input level
Figure 47. CCIR330 video line
The input level must not exceed the following values:
– First of all, the implementation of a proper ground plane in both sides of the PCB is
– Power supply bypass capacitors (4.7uF and ceramic 100pF) should be placed as
Proper termination of all inputs and outputs must be in accordance with output
termination resistors; in this way, the amplifier load will be resistive only, and the
stability of the amplifier will be improved.
All leads must be wide and as short as possible (especially for op-amp inputs and
outputs) in order to decrease parasitic capacitance and inductance.
For lower gain applications, care should be taken to avoid large feedback resistance
(>1k Ω ) in order to reduce the time constant of parasitic capacitances.
Choose component sizes as small as possible (SMD).
Finally, on output, the load capacitance must be negligible to maintain good stability.
You can put a serial resistance as close as possible to the output pin to minimize
capacitance.
negative peak: must be greater than -V
positive peak value: must be lower than +V
mandatory for high speed circuit applications to provide low inductance and low
resistance common return.
close as possible to the IC pins in order to improve high frequency bypassing and
reduce harmonic distortion. The power supply capacitors must be incorporated for
both the negative and the positive pins.
CC
+400mV.
CC
-400mV.
Testing Conditions
21/33

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