STM690AM6F STMicroelectronics, STM690AM6F Datasheet - Page 15

• Manufacturer Part Number: STM690AM6F
• Description: SUPERVISOR 5V SWITCH OVER 8SOIC
• Manufacturer: STMicroelectronics
• Type: Simple Reset/Power-On Resetr

Specifications of STM690AM6F

• Number Of Voltages Monitored: 1
• Output: Push-Pull, Totem Pole
• Reset: Active Low
• Reset Timeout: 140 ms Minimum
• Voltage - Threshold: 4.65V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Monitored Voltage: 1 V to 5.5 V
• Output Type: Active Low, Push-Pull
• Manual Reset: Not Resettable
• Watchdog: Watchdog
• Battery Backup Switching: Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Supply Current (typ): 60 uA
• Maximum Power Dissipation: 320 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: Yes
• Undervoltage Threshold: 4.5 V
• Overvoltage Threshold: 4.75 V
• Power-up Reset Delay (typ): 280 ms
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 497-3824-2

STM690A/692A/703/704/802/805/817/818/819
2.5
2.6
2.7
Figure 11. Chip-enable gating
V
CC
E
Chip-enable gating (STM818 only)
Internal gating of the chip-enable (E) signal prevents erroneous data from corrupting the
external CMOS RAM in the event of an undervoltage condition. The STM818 uses a series
transmission gate from E to E
asserted), the E transmission gate is enabled and passes all E transitions. When reset is
asserted, this path becomes disabled, preventing erroneous data from corrupting the CMOS
RAM. The short propagation delay from E to E
most µPs. If E is low when reset asserts, E
goes high) to permit the current WRITE cycle to complete. Connect E to V
Chip-enable input (STM818 only)
The chip-enable transmission gate is disabled and E is high impedance (disabled mode)
while reset is asserted. During a power-down sequence when V
threshold, the chip-enable transmission gate disables and E immediately becomes high
impedance if the voltage at E is high. If E is low when reset asserts, the chip-enable
transmission gate will disable 15 µs after reset asserts (see
current WRITE cycle to complete during power-down.
Any time a reset is generated, the chip-enable transmission gate remains disabled and E
remains high impedance (regardless of E activity) for the reset time-out period. When the
chip-enable transmission gate is enabled, the impedance of E appears as a 40
series with the load at E
gate depends on V
on E
the 50% point on E
For minimum propagation delay, minimize the capacitive load at E
impedance driver.
Chip-enable output (STM818 only)
When the chip-enable transmission gate is enabled, the impedance of E
a 40
gate is off and an active pull-up connects E
off when the transmission gate is enabled.
V
RST
CON
resistor in series with the source driving E. In the disabled mode, the transmission
. The chip-enable propagation delay is production tested from the 50% point on E to
CC
CON
, the source impedance of the drive connected to E, and the loading
using a 50
CON
COMPARE
. The propagation delay through the chip-enable transmission
CON
Doc ID 10522 Rev 10
E
CON
CONTROL
(see
OUTPUT
driver and a 50 pF load capacitance (see
Figure
CON
CON
11). During normal operation (reset not
CON
remains low for typically 15 µs (or until E
to V
Generator
t
rec
enables the STM818 to be used with
OUT
(see
Figure
Figure
CC
CON
12). This permits the
passes the reset
11). This pull-up turns
and use a low-output
RST
V
E
CON
OUT
CON
SS
is equivalent to
if unused.
Figure
Operation
resistor in
AI08802
39).
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