X4323S8I Intersil, X4323S8I Datasheet - Page 5

• Manufacturer Part Number: X4323S8I
• Description: IC CPU SUPRV 32K EE RST LO 8SOIC
• Manufacturer: Intersil
• Type: Simple Reset/Power-On Resetr

Specifications of X4323S8I

• Number Of Voltages Monitored: 1
• Output: Open Drain or Open Collector
• Reset: Active Low
• Reset Timeout: 100 ms Minimum
• Voltage - Threshold: 4.38V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PRINCIPLES OF OPERATION
Power-on Reset
Application of power to the X4323, X4325 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pin active. This signal provides several benefits.
– It prevents the system microprocessor from starting
– It prevents the processor from operating prior to sta-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
for
RESET/RESET allowing the system to begin operation.
LOW VOLTAGE MONITORING
During operation, the X4323, X4325 monitors the V
level and asserts RESET/RESET if supply voltage
falls
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The RESET/RESET signal remains active until the
voltage drops below 1V. It also remains active until
V
WATCHDOG TIMER
The Watchdog Timer circuit monitors the microproces-
sor activity by monitoring the SDA and SCL pins. The
microprocessor must toggle the SDA pin HIGH to
Figure 1. Set V
CC
SCL
SDA
to operate with insufficient voltage.
bilization of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
WP
returns and exceeds V
200ms
below
CC
exceeds the device V
0 1 2 3 4 5 6 7
a
TRIP
(nominal)
preset
A0h
Level Sequence (V
5
TRIP
minimum
the
for 200ms.
TRIP
0 1 2 3 4 5 6 7
circuit
threshold value
CC
V
V
P
TRIP
= 12-15V
= desired V
00h
releases
.
X4323, X4325
The
CC
TRIP
0 1 2 3 4 5 6 7
values WEL bit set)
LOW periodically, while SCL is HIGH (this is a start bit)
prior to the expiration of the watchdog time out period to
prevent a RESET/RESET signal. The state of two non-
volatile control bits in the Status Register determine
the watchdog timer period. The microprocessor can
change these watchdog bits, or they may be “locked”
by tying the WP pin HIGH.
EEPROM INADVERTENT WRITE PROTECTION
When RESET/RESET goes active as a result of a low
voltage condition or Watchdog Timer Time Out, any in-
progress communications are terminated. While
RESET/RESET is active, no new communications are
allowed and no nonvolatile write operation can start.
Nonvolatile writes in-progress when RESET/RESET
goes active are allowed to finish.
Additional protection mechanisms are provided with
memory Block Lock and the Write Protect (WP) pin.
These are discussed elsewhere in this document.
V
The X4323, X4325 is shipped with a standard V
threshold (V
over normal operating and storage conditions. How-
ever, in applications where the standard V
exactly right, or if higher precision is needed in the
V
adjusted. The procedure is described in the following
section, and uses the application of a nonvolatile con-
trol signal.
01h
CC
TRIP
THRESHOLD RESET PROCEDURE
value, the X4323, X4325 threshold may be
TRIP
) voltage. This value will not change
0 1 2 3 4 5 6 7
00h
TRIP
May 25, 2006
FN8122.1
is not
CC