S-80127BLMC-JEMT2G Seiko Instruments, S-80127BLMC-JEMT2G Datasheet - Page 18

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S-80127BLMC-JEMT2G

Manufacturer Part Number
S-80127BLMC-JEMT2G
Description
IC VOLT DETECTOR 100MS SOT23-5
Manufacturer
Seiko Instruments
Type
Simple Reset/Power-On Resetr
Datasheet

Specifications of S-80127BLMC-JEMT2G

Number Of Voltages Monitored
1
Output
Push-Pull, Totem Pole
Reset
Active Low
Reset Timeout
65 ms Minimum
Voltage - Threshold
2.7V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
SOT-23-5, SC-74A, SOT-25
Output Type
Push-Pull
Undervoltage Threshold
2.7 V
Power-up Reset Delay (typ)
100 ms
Supply Voltage (min)
0.95 V
Supply Voltage (max)
10 V
Supply Current (typ)
1.5 uA
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Description/function
Open-drain and CMOS output,
Detection Range
2.7 V +/- 2 %
Internal Hysteresis
Yes
Manual Reset
No
Operating Supply Voltage
0.7 V to 10 V
Watchdog
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
18
ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (INTERNAL DELAY TIME SETTING)
S-801 Series
2. Hysteresis Width (V
3. Delay Time (t
4. Through-type Current
Hysteresis width is the voltage difference between the detection voltage and the release voltage
(The voltage at point B−The voltage at point A=V
width prevents malfunction caused by noise on input signal.
Delay time is a time internally measured from the instant at which input voltage to the VDD pin
exceeds the release voltage (+V
delay time is fixed in each series distinguished by A, B and C.
The output of the OUT pin can be inverted in a short delay time (t
to Figure 16).
The through-type current refers to the current that flows instantaneously at the time of detection and
release of a voltage detector. The through-type current flows at a frequency of 20 kHz during release
delay time since the internal logic circuit operates.
S-801xxAx series: typ.
S-801xxBx series: typ.
S-801xxCx series: typ.
D
)
HYS
+V
)
V
DET
50 ms
100 ms
200 ms
Seiko Instruments Inc.
DET
) to the point at which the output of the OUT pin inverts. The
t
D2
Figure 16
at DS=”H”
t
HYS
D1
V
in Figure 11). The existence of the hysteresis
DD
D2
) by setting the DS pin High (Refer
OUT
Rev.4.0
_00

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