S-24CS64A0I-J8T1G Seiko Instruments, S-24CS64A0I-J8T1G Datasheet

no-image

S-24CS64A0I-J8T1G

Manufacturer Part Number
S-24CS64A0I-J8T1G
Description
IC EEPROM 64KBIT 400KHZ 8SOP
Manufacturer
Seiko Instruments
Datasheet

Specifications of S-24CS64A0I-J8T1G

Format - Memory
EEPROMs - Serial
Memory Type
EEPROM
Memory Size
64K (8K x 8)
Speed
400kHz
Interface
I²C, 2-Wire Serial
Voltage - Supply
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
S-24CS64A0I-J8T1G
Manufacturer:
SII Semiconductor Corporation
Quantity:
127 044
Part Number:
S-24CS64A0I-J8T1G
Manufacturer:
SEIKO
Quantity:
140
Caution This product is intended to use in general electronic devices such as consumer electronics,
Rev.4.2
• Low power consumption Standby : 5.0 µA Max. (V
• Operating voltage range Read :
• Page write :
• Sequential read
• Operating Frequency :
• Write disable function when power supply voltage is low
• Endurance:
• Data retention:
• Write protection :
• Lead-free products
Features
Packages
2-WIRE CMOS SERIAL E
8-Pin SOP (JEDEC)
8-Pin TSSOP
WLP
Package name
office equipment, and communications devices. Before using the product in medical
equipment or automobile equipment including car audio, keyless entry and engine control
unit, contact to SII is indispensable.
_00
Read :
Write :
32 bytes / page
400 kHz (V
10
10
*1. For each address (Word: 8 bits)
10 years (after rewriting 10
100 %
Please contact our sales office regarding the product with WLP package.
6
5
cycles / word
cycles / word
Package
FT008-A
FJ008-A
2
0.8 mA Max. (V
1.8 to 5.5 V
2.7 to 5.5 V
CC
PROM
= 2.7 to 5.5 V)
Seiko Instruments Inc.
*1
*1
(at +25°C) write capable,
(at +85°C)
CC
The S-24CS64A is a 2-wired, low power and wide
range operation 64 K-bit E
words × 8 bits.
Page write and sequential read are available.
CC
5
cycles / word at +85°C)
= 5.5 V)
= 5.5 V)
Drawing code
FJ008-D
FT008-E
Tape
2
PROM organized as 8192
S-24CS64A
FT008-E
FJ008-D
Reel
1

Related parts for S-24CS64A0I-J8T1G

S-24CS64A0I-J8T1G Summary of contents

Page 1

... SOP (JEDEC) 8-Pin TSSOP WLP Caution This product is intended to use in general electronic devices such as consumer electronics, office equipment, and communications devices. Before using the product in medical equipment or automobile equipment including car audio, keyless entry and engine control unit, contact to SII is indispensable. ...

Page 2

... CMOS SERIAL E S-24CS64A Pin Configurations 8-Pin SOP (JEDEC) Top view GND Figure 1 S-24CS64A0I-J8T1G 8-Pin TSSOP Top view GND Figure 2 S-24CS64A0I-T8T1G 2 2 PROM Pin No. Symbol 1 A0 VCC SCL 4 GND 5 SDA SDA 6 SCL VCC Remark See Dimensions for details of the package drawings. ...

Page 3

... A0 VCC SCL GND SDA Figure 3 S-24CS64A0I-H8Tx Remark Please contact our sales office regarding the product with WLP package. 2-WIRE CMOS SERIAL E Table 3 Pin No. Symbol 1 A0 Slave address input 2 VCC Power supply Write protection input 3 WP Connected to V Connected to GND: Protection invalid ...

Page 4

... CMOS SERIAL E S-24CS64A Block Diagram SCL Start / Stop Detector SDA Device Address Comparator PROM Serial Clock Controller LOAD COMP LOAD INC Address Counter Y Decoder D OUT Figure 4 Seiko Instruments Inc. Rev.4.2 _00 WP VCC GND Voltage Detector High-Voltage Generator Data Register 2 X Decoder ...

Page 5

... Power supply voltage Input voltage Output voltage Operating ambient temperature Storage temperature Caution The absolute maximum ratings are rated values exceeding which the product could suffer physical damage. These values must therefore not be exceeded under any conditions. Recommended Operating Conditions Item ...

Page 6

... Item Symbol Standby current consumption I SB Input leakage current I LI Output leakage current I LO Low level output voltage V OL Current address hold voltage PROM Table 4 400 kHz Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.    ...

Page 7

... Rev.4.2 _00 AC Electrical Characteristics Table 10 Measurement Conditions Input pulse voltage Input pulse rising / falling time Output judgement voltage Output load Item SCL clock frequency SCL clock time “L” SCL clock time “H” SDA output delay time SDA output hold time ...

Page 8

... CMOS SERIAL E S-24CS64A Write time SCL SDA D0 Write data 8 2 PROM Table 2 Item Symbol Min. t — WR Stop Condition Acknowledge Figure 7 Write Cycle Timing Seiko Instruments Inc. Unit Typ. Max. 6.0 10 Start Condition Rev.4.2 _00 ...

Page 9

... The SDA line is usually pulled up to the V devices. 3. SCL (Serial Clock Input) Pin The SCL pin is used for serial clock input. Since signals are processed at the rising or falling edge of the SCL clock input signal, attention should be paid to the rising time and falling time to conform to the specifications. ...

Page 10

... Every operation begins from a start condition. 2. Stop Condition Stop is identified by a low to high transition of the SDA line while the SCL line is stable at high. When a device receives a stop condition during a read sequence, the read operation is interrupted, and the device enters standby mode. ...

Page 11

... SDA 4. Acknowledge The unit of data transmission is 8 bits. During the 9th clock cycle period the receiver on the bus pulls down the SDA line to acknowledge the receipt of the 8-bit data. When a internal write cycle is in progress, the device does not generate an acknowledge. ...

Page 12

... To start communication, the master device on the system generates a start condition to the bus line. Next, the master device sends 7-bit device address and a 1-bit read / write instruction code on to the SDA bus. The 4 most significant bits of the device address are called the “Device Code”, and are fixed to “1010”. ...

Page 13

... The lower 5 bits of the word address are automatically incremented every time when the E receives 8-bit write data. If the size of the write data exceeds 32 bytes, the upper 8 bits of the word address remain unchanged, and the lower 5 bits are rolled over and previously received data will be overwritten ...

Page 14

... When the WP pin is connected to the GND, the write protection is invalid, and write operation in all memory area is available. Fix the level of the WP pin from the rising edge of SCL for loading the last write data (D0) until the end of the write time (10 ms max.). If the WP pin changes during this time, the address data being written at this time is not guaranteed ...

Page 15

... In the read operation the memory address counter in the E falling edge of the SCL clock for the 8th bit of the output data. In the write operation, on the other hand, the upper 8 bits of the memory address are left unchanged and are not incremented at the falling edge of the SCL clock for the 8th bit of the received data ...

Page 16

... PROM by these operations. Reception of write data does not follow in a dummy write whereas reception of write data follows in a byte write and in a page write. Since the memory address is loaded into the memory address counter by dummy write, the master device can read the data starting from the arbitrary memory address by transmitting a new start condition and performing the same operation in the current address read ...

Page 17

... Sequential Read 2 When the E PROM receives a 7-bit device address and a 1-bit read / write instruction code set to “1” following a start condition both in current and random read operations, it responds with an acknowledge. An 8-bit data is then sent from the E automatically incremented at the falling edge of the SCL clock for the 8th bit data. ...

Page 18

... Address Increment Timing The timing for the automatic address increment is the falling edge of the SCL clock for the 8th bit of the read data in read operation and the the falling edge of the SCL clock for the 8th bit of the received data in write operation. ...

Page 19

... PROM from malfunction due to an undefined output (high impedance) from the tri- state pin when the microprocessor is reset when the voltage drops. 2. I/O pin equivalent circuit The I/O pins of this IC do not include pull-up and pull-down resistors. The SDA pin is an open-drain output. The following shows the equivalent circuits. SCL ...

Page 20

... CMOS SERIAL E S-24CS64A WP A0, A1 PROM Figure 23 WP Pin Figure 24 A0, A1, A2 Pin Seiko Instruments Inc. Rev.4.2 _00 ...

Page 21

... If a communication interruption occurs in the E software. For example, even if a reset signal is input to the microprocessor, the internal circuit of the E reset as long as the stop condition is not input to the E same status and cannot shift to the next operation. This symptom applies to the case when only the microprocessor is reset when the power supply voltage drops ...

Page 22

... Raising power supply voltage Raise the power supply voltage, starting at 0.2 V maximum, so that the voltage reaches the power supply voltage to be used within the time defined by t For example, when the power supply voltage to be used is 5 The power supply voltage must be raised within 200 ms ...

Page 23

... E power-on-clear operation conditions conditions of E PROM, refer to 5.1 Raising power supply voltage . If the power-on-clear circuit does not operate, match the phase (reset) so that the internal E is normally reset. The statuses of the E when phase is matched (reset) are the same. 5.0 4.0 ...

Page 24

... S-24CS64A 5.2 Wait for the initialization sequence to end 2 The E PROM executes initialization during the time that the supply voltage is increasing to its normal value. All instructions must wait until after initialization. The relationship between the initialization time (t ) and rise time ( shown in Figure 28 . ...

Page 25

... SDA pin and SCL pin noise suppression time The S-24CS64A includes a built-in low-pass filter to suppress noise at the SDA and SCL pins. This means that if the power supply voltage is 5.0 V, noise with a pulse width of 160 ns or less can be suppressed. The guaranteed for details, refer to noise suppression time (t ...

Page 26

... When write data is input more than defined page size at page write operation, for example, S-24CS64A (which can be executed 32-byte page write) is received data more than 33 byte, 8-bit data of the 33rd byte is over written to the first byte in the same page. Data over the capacity of page address cannot be written. 10. Trap: Severe environments Absolute maximum ratings: Do not operate these ICs in excess of the absolute max ratings, as listed on the data sheet ...

Page 27

... In this package, the overcoat of the resin of translucence is carried out on the side of device area. Keep it mind that it may affect the characteristic of a device when exposed a device in the bottom of a high light source ...

Page 28

... DATA=0101 500 I CC1 400 (µA) 300 200 100 ( PROM 1.2 Current consumption (READ) I CC1  Ambient temperature Ta I CC1 (µA) 85 1.4 Current consumption (READ) I CC1  Power supply voltage V I CC1 (µA) 85 1.6 Current consumption (READ) I CC1  Clock frequency f CC ...

Page 29

... Rev.4.2 _00 1.7 Current consumption (PROGRAM) I  Ambient temperature 1.5 I CC2 (mA) 1.0 0.5 0 – (°C) 1.9 Current consumption (PROGRAM) I  Ambient temperature Ta =2 1.5 I CC2 1.0 (mA) 0.5 0 – (°C) 1.11 Standby current consumption I  Ambient temperature (µA) 1.0 0 – ...

Page 30

... CMOS SERIAL E S-24CS64A 1.13 Input leakage current I  Ambient temperature Ta =5 SDA, SCL, WP=5 (µA) 0.5 0 – (°C) 1.15 Output leakage current I  Ambient temperature Ta =5 SDA=5 (µA) 0.5 0 – (°C) 1.17 Low level output voltage V  Low level output current I Ta=25° ...

Page 31

... V (V) CC 1.21 Low input inversion voltage V  Power supply voltage V Ta=25°C SDA, SCL 3.0 2 (V) 1 (V) CC 1.23 Low power supply detection voltage −V  Ambient temperature Ta 2.0 −V DET (V) 1 – (°C) 1.20 High input inversion voltage 3.0 2 (V) 1.0 ...

Page 32

... Ta=25° MAX. (Hz) 100k 10k (V) CC  Ambient temperature Ta 2.3 Write time (ms – (°C) 2.5 SDA output delay time t  Ambient temperature (µs) 0.5 0 – (° PROM 2.2 Write time t MAX (ms) 5 2.4 Write time (ms) 85 2.6 SDA output delay time t AA  ...

Page 33

... Rev.4.2 _00 2.7 SDA output delay time t  Ambient temperature (µs) 0 –40 0 Ta(°C) AA Seiko Instruments Inc. 2-WIRE CMOS SERIAL E S-24CS64A 2 PROM 33 ...

Page 34

... Product Name Structure 1. 8-Pin SOP(JEDEC), 8-Pin TSSOP Packages S-24CS64A 0I - xxxx G 2. WLP Package S-24CS64A 0I Remark Please contact our sales office regarding the product with WLP package PROM Package name (abbreviation) and IC packing specifications J8T1: 8-Pin SOP (JEDEC), Tape T8T1: 8-Pin TSSOP, Tape Fixed ...

Page 35

...

Page 36

...

Page 37

...

Page 38

...

Page 39

...

Page 40

...

Page 41

... Use of the information described herein for other purposes and/or reproduction or copying without the express permission of Seiko Instruments Inc. is strictly prohibited. The products described herein cannot be used as part of any device or equipment affecting the human body, such as exercise equipment, medical equipment, security systems, gas equipment, or any apparatus installed in airplanes and other vehicles, without prior written permission of Seiko Instruments Inc ...

Related keywords