S-80943CLMC-G7DT2G Seiko Instruments, S-80943CLMC-G7DT2G Datasheet - Page 13
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S-80943CLMC-G7DT2G
Manufacturer Part Number
S-80943CLMC-G7DT2G
Description
IC VOLT DETECTOR 4.3V SOT23-5
Manufacturer
Seiko Instruments
Type
Simple Reset/Power-On Resetr
Datasheet
1.S-80913CLPF-G6HTFG.pdf
(36 pages)
Specifications of S-80943CLMC-G7DT2G
Number Of Voltages Monitored
1
Output
Push-Pull, Totem Pole
Reset
Active Low
Reset Timeout
18 ms Minimum
Voltage - Threshold
4.3V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
SOT-23-5, SC-74A, SOT-25
Output Type
Push-Pull
Undervoltage Threshold
4.3 V
Power-up Reset Delay (typ)
Adj
Supply Voltage (min)
0.7 V
Supply Voltage (max)
10 V
Supply Current (typ)
1.3 uA
Operating Temperature Range
- 40 C to + 85 C
Mounting Style
SMD/SMT
Description/function
Open-drain and CMOS output,
Detection Range
4.3 V +/- 2 %
Internal Hysteresis
Yes
Manual Reset
No
Operating Supply Voltage
0.7 V to 10 V
Watchdog
No
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Rev.4.0
ULTRA-SMALL PACKAGE HIGH-PRECISION VOLTAGE DETECTOR WITH DELAY CIRCUIT (EXTERNAL DELAY TIME SETTING)
2. Delay Circuit
The delay circuit delays the output signal from the time at which the power voltage (V
release voltage (+V
the detection voltage (−V
of the built-in constant current (approx. 100 nA ) and the attached external capacitor (C
from the following equation.
Delay coefficient: (25°C)
Caution 1. When the CD pin is open, a double pulse shown in Figure 16 may appear at release. To
t
Detection voltage −V
Detection voltage −V
D
(ms)=Delay coefficient×C
_00
Nch open-drain output products: Min. 4.3,
CMOS output products:
3. There is no limit for the capacitance of the external capacitor (C
2. Print circuit board layout should be made in such a way that no current flows into or
flows from the CD pin since the impedance of the CD pin is high, otherwise correct
delay time cannot be provided.
current of the capacitor can be ignored against the built-in constant current value.
Leakage current causes deviation in delay time. When the leakage current is larger
than the built-in constant current, no release takes place.
avoid the double pulse, attach 20 pF or larger capacitor to the CD pin. Do not apply
voltage to the CD pin.
DET
Hysteresis width (V
) when V
DET
DET
DET
≤ 1.4 V
≥ 1.5 V
) (Refer to Figure 15). The delay time (t
D
DD
(nF)
is turned on. The output signal is not delayed when the V
HYS
Min. 0.57, Typ. 0.77, Max. 0.96
Min. 3.8,
V
Seiko Instruments Inc.
)
DD
(1) (2)
Figure 15 Operation 2
V
SS
V
OUT
A
(3)
Typ. 5.7,
Typ. 5.1,
(4)
Figure 16
B
(5)
t
D
Release volatage (+V
Detection voltage (−V
Output from OUT pin
V
Minimum operating voltage
V
DD
SS
Max. 7.2
Max. 6.4
time
D
) is determined by the time constant
D
DET
DET
) as long as the leakage
)
)
S-809xxC Series
D
), and calculated
DD
) exceeds the
DD
goes below
13