X40415V8IZ-BT1 Intersil, X40415V8IZ-BT1 Datasheet - Page 12

• Manufacturer Part Number: X40415V8IZ-BT1
• Description: IC VOLTAGE MON DUAL W/SUP 8TSSOP
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40415V8IZ-BT1

• Number Of Voltages Monitored: 2
• Output: Open Drain or Open Collector
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 1.3V, 2.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A similar operation called “Set Current Address” where
the device will perform this operation if a stop is issued
instead of the second start shown in Figure 15. The
device will go into standby mode after the stop and all
bus activity will be ignored until a start is detected.
This operation loads the new address into the address
counter. The next Current Address Read operation will
read from the newly loaded address. This operation
could be useful if the master knows the next address it
needs to read, but is not ready for the data.
Sequential Read
Sequential reads can be initiated as either a current
address read or random address read. The first Data
Byte is transmitted as with the other modes; however,
the master now responds with an acknowledge, indicat-
ing it requires additional data. The device continues to
output data for each acknowledge received. The master
terminates the read operation by not responding with an
acknowledge and then issuing a stop condition.
The data output is sequential, with the data from
address n followed by the data from address n + 1. The
address counter for read operations increments through
all page and column addresses, allowing the entire
memory contents to be serially read during one opera-
tion. At the end of the address space the counter “rolls
over” to address 0000
put data for each acknowledge received. See Figure 15
for the acknowledge and data transfer sequence.
SERIAL DEVICE ADDRESSING
Memory Address Map
CR, Control Register, CR7: CR0
Address: 1FF
Figure 14. Current Address Read Sequence
hex
H
and the device continues to out-
12
Signals from
Signals from
the Master
the Slave
SDA Bus
X40410, X40411, X40414, X40415
S
a
t
r
t
1 0 1 0
Address
Slave
0
0
1
FDR, Fault DetectionRegister, FDR7: FDR0
Address: 0FF
General Purpose Memory Organization, A8:A0
Address: 00h to 1FFh
General Purpose Memory Array Configuration
Slave Address Byte
Following a start condition, the master must output a
Slave Address Byte. This byte consists of several parts:
– a device type identifier that is always ‘101x’. Where
– next two bits are ‘0’.
– next bit that becomes the MSB of the address.
Figure 13. X40410/11 Addressing
Memory Address
General Purpose Memory
Control Register
Fault Detection Register
General Purpose Memory
Control Register
Fault Detection Register
x=0 is for Array, x=1 is for Control Register or Fault
Detection Register.
Data
A8:A0
0FFh
1FFh
000h
100h
hex
Lower 256 bytes
Upper 256 bytes
S
o
p
t
Slave Byte
Word Address
A7
1
1
1
1
1
A6 A5 A4
0
0
0
1
1
1
1
1
1
1
0
1
1
1
1
Block Protect Option
0
0
0
A3 A2
1
1
0
0
0
1
1
March 28, 2005
A8 R/W
1
0
A1 A0
1
1
FN8116.0
R/W
R/W
1
1