X40415V8IZ-BT1 Intersil, X40415V8IZ-BT1 Datasheet - Page 3

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X40415V8IZ-BT1

Manufacturer Part Number
X40415V8IZ-BT1
Description
IC VOLTAGE MON DUAL W/SUP 8TSSOP
Manufacturer
Intersil
Type
Multi-Voltage Supervisorr
Datasheet

Specifications of X40415V8IZ-BT1

Number Of Voltages Monitored
2
Output
Open Drain or Open Collector
Reset
Active High
Reset Timeout
Adjustable/Selectable
Voltage - Threshold
1.3V, 2.6V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
8-TSSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
PIN DESCRIPTION
PRINCIPLES OF OPERATION
Power-On Reset
Application of power to the X40410/11/14/15 activates a
Power-on Reset Circuit that pulls the RESET/RESET
pins active. This signal provides several benefits.
– It prevents the system microprocessor from starting to
– It prevents the processor from operating prior to stabili-
– It allows time for an FPGA to download its configura-
– It prevents communication to the EEPROM, greatly
When V
t
(X40411) and RESET (X40410) pin allowing the system
to begin operation.
Low Voltage V
During operation, the X40410/11/14/15 monitors the
V
falls
RESET/RESET signal prevents the microprocessor
from operating in a power fail or brownout condition.
The V1FAIL signal remains active until the voltage
drops below 1V. It also remains active until V
and exceeds V
Low Voltage V2 Monitoring
The X40410/11/14/15 also monitors a second voltage
level and asserts V2FAIL if the voltage falls below a
preset minimum V
ORed with RESET to prevent the microprocessor from
operating in a power fail or brownout condition or used to
interrupt the microprocessor with notification of an
impending power failure. For the X40410/11 the V2FAIL
signal remains active until the V
falling). It also remains active until V2MON returns and
exceeds V
monitors the power supply connected to the V2MON pin.
If V
PURST
SOIC TSSOP
CC
operate with insufficient voltage.
zation of the oscillator.
tion prior to initialization of the circuit.
reducing the likelihood of data corruption on power-up.
6
7
8
CC
level and asserts RESET/RESET if supply voltage
Pin
= 0, V2MON can still be monitored.
below
CC
(selectable) the circuit releases the RESET
exceeds the device V
TRIP2
8
1
2
TRIP1
CC
a
by 0.2V. This voltage sense circuitry
Name
WDO
(V1 Monitoring)
SCL
V
TRIP2
preset
CC
for
(Continued)
t
PURST
. The V2FAIL signal is either
Serial Clock. The Serial Clock controls the serial bus timing for data input and output.
WDO Output. WDO is an active LOW, open drain output which goes active whenever the watch-
dog timer goes active.
Supply Voltage
3
minimum
.
CC
TRIP1
drops below 1V (V
threshold value for
X40410, X40411, X40414, X40415
V
TRIP1
CC
.
returns
The
CC
For the X40414/15 devices, the V2FAIL signal remains
actice until V
until V2MON returns and exceeds V
circuitry is powered by V
be monitored.
Figure 1. Two Uses of Multiple Voltage Monitoring
Notice: No external components required to monitor two voltages.
Unreg.
Supply
Resistors selected so 3V appears on V2MON when unregulated
Function
6–10V
1M
1M
CC
1.2V
3.3V
Reg
Reg
drops below 1Vx and remains active
Reg
5V
supply reaches 6V.
V
V2MON
CC
CC
X40414-C
V2MON
(2.9V)
X40411-A
V
. If V
CC
RESET
V2FAIL
RESET
V2FAIL
CC
= 0, V2MON cannot
V
TRIP2
CC
V
CC
. This sense
V2MON
March 28, 2005
System
Reset
System
Reset
FN8116.0

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