X40010S8I-A Intersil, X40010S8I-A Datasheet - Page 5

• Manufacturer Part Number: X40010S8I-A
• Description: IC VOLTAGE MONITOR DUAL 8-SOIC
• Manufacturer: Intersil
• Type: Multi-Voltage Supervisorr

Specifications of X40010S8I-A

• Number Of Voltages Monitored: 2
• Output: Push-Pull, Totem Pole
• Reset: Active High
• Reset Timeout: Adjustable/Selectable
• Voltage - Threshold: 2.9V, 4.6V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Resetting the V
To reset a V
age (Vp) to the WDO pin before a START condition is
set up on SDA. Next, issue on the SDA pin the Slave
Address A0h followed by the Byte Address 03h for
V
Data Byte in order to reset V
lowing a valid write operation initiates the program-
ming sequence. Pin WDO must then be brought LOW
to complete the operation.
After being reset, the value of V
nal value of 1.7V or lesser.
Note: This operation does not corrupt the memory
array.
CONTROL REGISTER
The Control Register provides the user a mechanism
for changing the Block Lock and Watchdog Timer set-
tings. The Block Lock and Watchdog Timer bits are
nonvolatile and do not change when power is removed.
The Control Register is accessed with a special pream-
ble in the slave byte (1011) and is located at address
1FFh. It can only be modified by performing a byte write
operation directly to the address of the register and only
Figure 4. Sample V
TRIP1
V
Adj.
TRIP1
and 0Bh for V
TRIPx
TRIPx
voltage, apply the programming volt-
TRIP
V
Adj.
Voltage
TRIP2
TRIP2
Reset Circuit
5
V2FAIL
, followed by 00h for the
TRIPx
TRIPx
RESET
. The STOP bit fol-
4.7K
becomes a nomi-
X40010, X40011, X40014, X40015
1
3
2
4
X4001x
SOIC
one data byte is allowed for each register write opera-
tion. Prior to writing to the Control Register, the WEL
and RWEL bits must be set using a two step process,
with the whole sequence requiring 3 steps. See "Writing
to the Control Registers" on page 7.
The user must issue a stop, after sending this byte to
the register, to initiate the nonvolatile cycle that stores
WD1, WD0, PUP1, PUP0, BP1, and BP0. The
X40010/11/14/15 will not acknowledge any data bytes
written after the first byte is entered.
The state of the Control Register can be read at any
time by performing a random read at address 01Fh,
using the special preamble. Only one byte is read by
each register read operation. The master should sup-
ply a stop condition to be consistent with the bus pro-
tocol, but a stop is not required to end this operation.
RWEL: Register Write Enable Latch (Volatile)
The RWEL bit must be set to “1” prior to a write to the
Control Register.
PUP1 WD1 WD0
8
7
6
5
7
6
5
Adjust
Run
BP
4
V
P
3
0
SCL
SDA
RWEL WEL PUP0
2
µC
1
March 28, 2005
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